53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module scrambler_tb;
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parameter VCD_FILE = "scrambler_tb.vcd";
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`include "tb_base.v"
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reg [31:0] data_in;
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reg [31:0] data_out_expected;
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wire [31:0] data_scrambled;
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wire [31:0] data_out;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data_in <= 'h03020100;
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end else begin
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data_in <= data_in + {4{8'h04}};
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end
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end
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jesd204_scrambler #(
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.DESCRAMBLE(0)
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) i_scrambler (
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.clk(clk),
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.reset(reset),
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.enable(1'b1),
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.data_in(data_in),
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.data_out(data_scrambled));
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jesd204_scrambler #(
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.DESCRAMBLE(1)
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) i_descrambler (
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.clk(clk),
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.reset(reset),
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.enable(1'b1),
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.data_in(data_scrambled),
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.data_out(data_out));
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always @(posedge clk) begin
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if (data_in != data_out && failed == 1'b0) begin
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failed <= 1'b1;
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end
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end
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endmodule
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