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Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 		2014-03-24 13:07:48 +02:00
..
system_bd.tcl VC707 basesys: General fixes, actual status: working 2014-03-24 13:07:48 +02:00
system_project.tcl Initial check in of VC707 base project 2014-03-10 17:26:17 +02:00
system_top.v Initial check in of VC707 base project 2014-03-10 17:26:17 +02:00