f43b5d707e
Modified ZED constraints to 250 MHz for the clock from AD9361 |
||
---|---|---|
.. | ||
system_bd.tcl | ||
system_constr.xdc | ||
system_project.tcl | ||
system_top.v |
f43b5d707e
Modified ZED constraints to 250 MHz for the clock from AD9361 |
||
---|---|---|
.. | ||
system_bd.tcl | ||
system_constr.xdc | ||
system_project.tcl | ||
system_top.v |