fa9d94bfe8
The ADI transport layer peripherals expect the first octet to be in the LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders the octets the other way around though, first octet in the MSBs and last octet in the LSBS. Currently this is handled by having each transport layer peripheral swap the octets around when it is connected to the Altera JESD204 core. Change this so that rather than having to do the data swizzling in every in every transport layer peripheral perform it at the input/output of the link layer peripheral inside the generated block. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| axi_ad9152.v | ||
| axi_ad9152_channel.v | ||
| axi_ad9152_constr.xdc | ||
| axi_ad9152_core.v | ||
| axi_ad9152_hw.tcl | ||
| axi_ad9152_if.v | ||
| axi_ad9152_ip.tcl | ||