131 lines
4.2 KiB
VHDL
131 lines
4.2 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- In this HDL repository, there are many different and unique modules, consisting
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-- of various HDL (Verilog or VHDL) components. The individual modules are
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-- developed independently, and may be accompanied by separate and unique license
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-- terms.
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--
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-- The user should read each of these license terms, and understand the
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-- freedoms and responsabilities that he or she has by using this source/core.
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--
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-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
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-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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-- A PARTICULAR PURPOSE.
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--
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-- Redistribution and use of source or resulting binaries, with or without modification
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-- of this file, are permitted under one of the following two license terms:
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory
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-- of this repository (LICENSE_GPL2), and also online at:
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-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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--
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-- OR
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--
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-- 2. An ADI specific BSD license, which can be found in the top level directory
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-- of this repository (LICENSE_ADIBSD), and also on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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-- This will allow to generate bit files and not release the source code,
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-- as long as it attaches to an ADI device.
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity i2s_clkgen is
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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enable : in Boolean ; -- Enable clockgen
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tick : in std_logic;
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bclk_div_rate : in natural range 0 to 255;
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lrclk_div_rate : in natural range 0 to 255;
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bclk : out std_logic; -- Bit Clock
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lrclk : out std_logic; -- Frame Clock
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channel_sync : out std_logic;
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frame_sync : out std_logic
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);
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end i2s_clkgen;
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architecture Behavioral of i2s_clkgen is
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signal reset_int : Boolean;
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signal prev_bclk_div_rate : natural range 0 to 255;
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signal prev_lrclk_div_rate : natural range 0 to 255;
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signal bclk_count : natural range 0 to 255;
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signal lrclk_count : natural range 0 to 255;
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signal bclk_int : std_logic;
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signal lrclk_int : std_logic;
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signal lrclk_tick : Boolean;
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begin
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reset_int <= resetn = '0' or not enable;
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bclk <= bclk_int;
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lrclk <= lrclk_int;
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-----------------------------------------------------------------------------------
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-- Serial clock generation BCLK_O
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-----------------------------------------------------------------------------------
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bclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_bclk_div_rate <= bclk_div_rate;
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if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
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bclk_int <= '1';
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bclk_count <= bclk_div_rate;
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else
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if tick = '1' then
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if bclk_count = bclk_div_rate then
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bclk_count <= 0;
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bclk_int <= not bclk_int;
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else
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bclk_count <= bclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process bclk_gen;
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lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
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channel_sync <= '1' when lrclk_count = 1 else '0';
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frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
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-----------------------------------------------------------------------------------
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-- Frame clock generator LRCLK_O
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-----------------------------------------------------------------------------------
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lrclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_lrclk_div_rate <= lrclk_div_rate;
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-- Reset
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if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
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lrclk_int <= '1';
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lrclk_count <= lrclk_div_rate;
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else
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if lrclk_tick then
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if lrclk_count = lrclk_div_rate then
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lrclk_count <= 0;
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lrclk_int <= not lrclk_int;
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else
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lrclk_count <= lrclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process lrclk_gen;
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end Behavioral;
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