82 lines
3.6 KiB
Verilog
82 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// This IP allows the interpolation by 8 of the data from the input
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// The interpolation filter is implemented using a fir_compiler IP from
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// Xilinx.
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_fir_int (
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input aclk,
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input s_axis_data_tvalid,
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output s_axis_data_tready,
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input [31:0] s_axis_data_tdata,
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output [15:0] channel_0,
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output [15:0] channel_1,
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output m_axis_data_tvalid,
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input interpolate,
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input dac_read);
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wire [31:0] m_axis_data_tdata_s;
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reg s_axis_data_tready_r;
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reg [2:0] ready_counter;
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always @(posedge aclk) begin
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ready_counter <= ready_counter + 1;
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if (ready_counter == 0) begin
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s_axis_data_tready_r <= 1'b1;
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end else begin
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s_axis_data_tready_r <= 1'b0;
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end
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end
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assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16],1'b0,m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata;
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assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read;
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fir_interp interpolator (
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.aclk(aclk),
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.s_axis_data_tvalid(s_axis_data_tvalid),
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.s_axis_data_tready(),
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.s_axis_data_tdata(s_axis_data_tdata),
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.m_axis_data_tvalid(m_axis_data_tvalid),
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.m_axis_data_tdata(m_axis_data_tdata_s)
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);
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endmodule // util_fir_int
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