106 lines
3.8 KiB
Verilog
106 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module mdc_mdio #(
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parameter PHY_AD = 5'b10000) (
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input mdio_mdc,
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input mdio_in_w,
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input mdio_in_r,
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output reg [ 1:0] speed_select,
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output reg duplex_mode);
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localparam IDLE = 2'b01;
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localparam ACQUIRE = 2'b10;
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wire preamble;
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reg [ 1:0] current_state = IDLE;
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reg [ 1:0] next_state = IDLE;
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reg [31:0] data_in = 32'h0;
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reg [31:0] data_in_r = 32'h0;
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reg [ 5:0] data_counter = 6'h0;
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assign preamble = &data_in;
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always @(posedge mdio_mdc) begin
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current_state <= next_state;
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data_in <= {data_in[30:0], mdio_in_w};
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if (current_state == ACQUIRE) begin
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data_counter <= data_counter + 1;
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end else begin
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data_counter <= 0;
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end
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if (data_counter == 6'h1f) begin
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if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin
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speed_select <= data_in_r[16:15] ;
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duplex_mode <= data_in_r[14];
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end
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end
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end
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always @(negedge mdio_mdc) begin
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data_in_r <= {data_in_r[30:0], mdio_in_r};
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end
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always @(*) begin
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case (current_state)
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IDLE: begin
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if (preamble == 1 && mdio_in_w == 0) begin
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next_state <= ACQUIRE;
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end else begin
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next_state <= IDLE;
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end
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end
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ACQUIRE: begin
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if (data_counter == 6'h1f) begin
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next_state <= IDLE;
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end else begin
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next_state <= ACQUIRE;
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end
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end
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default: begin
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next_state <= IDLE;
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end
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endcase
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end
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endmodule
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