273 lines
9.6 KiB
Verilog
273 lines
9.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// hps
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output [ 14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_ck_p,
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output ddr3_ck_n,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_reset_n,
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inout [ 39:0] ddr3_dq,
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inout [ 4:0] ddr3_dqs_p,
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inout [ 4:0] ddr3_dqs_n,
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output ddr3_odt,
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output [ 4:0] ddr3_dm,
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input ddr3_oct_rzqin,
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output eth1_tx_clk,
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output eth1_tx_ctl,
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output eth1_txd0,
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output eth1_txd1,
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output eth1_txd2,
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output eth1_txd3,
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input eth1_rx_clk,
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input eth1_rx_ctl,
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input eth1_rxd0,
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input eth1_rxd1,
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input eth1_rxd2,
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input eth1_rxd3,
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output eth1_mdc,
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inout eth1_mdio,
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output qspi_ss0,
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output qspi_clk,
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inout qspi_io0,
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inout qspi_io1,
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inout qspi_io2,
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inout qspi_io3,
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output sdio_clk,
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inout sdio_cmd,
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inout sdio_d0,
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inout sdio_d1,
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inout sdio_d2,
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inout sdio_d3,
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input usb1_clk,
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output usb1_stp,
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input usb1_dir,
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input usb1_nxt,
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inout usb1_d0,
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inout usb1_d1,
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inout usb1_d2,
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inout usb1_d3,
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inout usb1_d4,
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inout usb1_d5,
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inout usb1_d6,
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inout usb1_d7,
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input uart0_rx,
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output uart0_tx,
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// board gpio
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output [ 3:0] gpio_bd_o,
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input [ 7:0] gpio_bd_i,
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// i2c
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inout fmca_scl,
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inout fmca_sda,
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// lane interface
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input ref_clk,
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input [ 3:0] rx_data,
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output rx_sync,
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output rx_sysref,
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// spi
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output spi_csn,
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output spi_clk,
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inout spi_sdio);
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// internal signals
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wire sys_cpu_clk;
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wire sys_dma_clk;
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wire sys_rstn;
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wire rx_clk;
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wire [ 3:0] rx_ip_sof;
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wire [127:0] rx_ip_data;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire spi_mosi;
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wire spi_miso;
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wire fmca_scl_oe;
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wire fmca_sda_oe;
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// i2c
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assign fmca_scl = (fmca_scl_oe == 1'b1) ? 1'b0 : 1'bz;
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assign fmca_sda = (fmca_sda_oe == 1'b1) ? 1'b0 : 1'bz;
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// gpio
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assign gpio_i[63: 8] = gpio_o[63:8];
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assign gpio_i[ 7: 0] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[11:8];
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// sysref
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ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
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.core_clk (rx_clk),
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.sysref_en (gpio_o[32]),
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.sysref_out (rx_sysref));
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// instantiations
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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system_bd i_system_bd (
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.rx_core_clk_clk (rx_clk),
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.rx_data_0_rx_serial_data (rx_data[0]),
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.rx_data_1_rx_serial_data (rx_data[1]),
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.rx_data_2_rx_serial_data (rx_data[2]),
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.rx_data_3_rx_serial_data (rx_data[3]),
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.rx_ip_data_data (rx_ip_data),
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.rx_ip_data_valid (),
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.rx_ip_data_ready (1'b1),
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.rx_ip_data_0_data (rx_ip_data[63:0]),
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.rx_ip_data_0_valid (1'b1),
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.rx_ip_data_0_ready (),
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.rx_ip_data_1_data (rx_ip_data[127:64]),
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.rx_ip_data_1_valid (1'b1),
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.rx_ip_data_1_ready (),
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.rx_ip_sof_export (rx_ip_sof),
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.rx_ip_sof_0_export (rx_ip_sof),
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.rx_ip_sof_1_export (rx_ip_sof),
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.rx_ref_clk_clk (ref_clk),
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.rx_sync_export (rx_sync),
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.rx_sysref_export (rx_sysref),
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.sys_clk_clk (sys_cpu_clk),
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.sys_dma_clk_clk (sys_dma_clk),
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.sys_dma_rst_reset_n (sys_rstn),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_hps_cpu_clk_clk (sys_cpu_clk),
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.sys_hps_ddr3_mem_a (ddr3_a),
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.sys_hps_ddr3_mem_ba (ddr3_ba),
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.sys_hps_ddr3_mem_ck (ddr3_ck_p),
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.sys_hps_ddr3_mem_ck_n (ddr3_ck_n),
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.sys_hps_ddr3_mem_cke (ddr3_cke),
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.sys_hps_ddr3_mem_cs_n (ddr3_cs_n),
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.sys_hps_ddr3_mem_ras_n (ddr3_ras_n),
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.sys_hps_ddr3_mem_cas_n (ddr3_cas_n),
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.sys_hps_ddr3_mem_we_n (ddr3_we_n),
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.sys_hps_ddr3_mem_reset_n (ddr3_reset_n),
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.sys_hps_ddr3_mem_dq (ddr3_dq),
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.sys_hps_ddr3_mem_dqs (ddr3_dqs_p),
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.sys_hps_ddr3_mem_dqs_n (ddr3_dqs_n),
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.sys_hps_ddr3_mem_odt (ddr3_odt),
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.sys_hps_ddr3_mem_dm (ddr3_dm),
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.sys_hps_ddr3_oct_rzqin (ddr3_oct_rzqin),
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.sys_hps_dma_clk_clk (sys_dma_clk),
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.sys_hps_i2c0_out_data (fmca_sda_oe),
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.sys_hps_i2c0_sda (fmca_sda),
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.sys_hps_i2c0_clk_clk (fmca_scl_oe),
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.sys_hps_i2c0_scl_clk (fmca_scl),
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.sys_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
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.sys_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
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.sys_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
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.sys_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
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.sys_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
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.sys_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
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.sys_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
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.sys_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
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.sys_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
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.sys_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
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.sys_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
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.sys_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
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.sys_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
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.sys_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
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.sys_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
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.sys_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
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.sys_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
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.sys_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
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.sys_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
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.sys_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
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.sys_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
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.sys_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
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.sys_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
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.sys_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
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.sys_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
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.sys_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
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.sys_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
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.sys_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
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.sys_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
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.sys_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
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.sys_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
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.sys_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
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.sys_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
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.sys_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
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.sys_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
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.sys_hps_io_hps_io_usb1_inst_STP (usb1_stp),
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.sys_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
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.sys_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
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.sys_hps_io_hps_io_uart0_inst_RX (uart0_rx),
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.sys_hps_io_hps_io_uart0_inst_TX (uart0_tx),
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.sys_hps_rstn_reset_n (sys_rstn),
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.sys_hps_spim0_txd (spi_mosi),
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.sys_hps_spim0_rxd (spi_miso),
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.sys_hps_spim0_ss_in_n (1'b1),
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.sys_hps_spim0_ssi_oe_n (spi_csn),
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.sys_hps_spim0_ss_0_n (),
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.sys_hps_spim0_ss_1_n (),
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.sys_hps_spim0_ss_2_n (),
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.sys_hps_spim0_ss_3_n (),
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.sys_hps_spim0_sclk_clk (spi_clk),
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.sys_rst_reset_n (sys_rstn));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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