166 lines
6.5 KiB
Verilog
166 lines
6.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// A simple asymetric memory. The write and read memory space must have the same size.
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// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
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`timescale 1ns/100ps
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module ad_mem_asym #(
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parameter A_ADDRESS_WIDTH = 8,
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parameter A_DATA_WIDTH = 256,
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parameter B_ADDRESS_WIDTH = 10,
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parameter B_DATA_WIDTH = 64) (
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input clka,
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input wea,
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input [A_ADDRESS_WIDTH-1:0] addra,
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input [A_DATA_WIDTH-1:0] dina,
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input clkb,
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input [B_ADDRESS_WIDTH-1:0] addrb,
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output reg [B_DATA_WIDTH-1:0] doutb);
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localparam MEM_ADDRESS_WIDTH = (A_ADDRESS_WIDTH > B_ADDRESS_WIDTH) ? A_ADDRESS_WIDTH : B_ADDRESS_WIDTH;
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localparam MEM_DATA_WIDTH = (A_DATA_WIDTH > B_DATA_WIDTH) ? B_DATA_WIDTH : A_DATA_WIDTH;
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localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;
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localparam MEM_RATIO = (A_DATA_WIDTH > B_DATA_WIDTH) ? A_DATA_WIDTH/B_DATA_WIDTH : B_DATA_WIDTH/A_DATA_WIDTH;
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localparam MEM_IO_COMP = (A_DATA_WIDTH > B_DATA_WIDTH) ? 1'b1 : 1'b0;
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// internal registers
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reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1];
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// write interface options
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generate if (MEM_IO_COMP == 0) begin
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[addra] <= dina;
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end
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 2)) begin
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[{addra, 1'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
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m_ram[{addra, 1'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
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end
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 4)) begin
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[{addra, 2'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
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m_ram[{addra, 2'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
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m_ram[{addra, 2'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
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m_ram[{addra, 2'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
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end
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 1) && (MEM_RATIO == 8)) begin
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always @(posedge clka) begin
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if (wea == 1'b1) begin
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m_ram[{addra, 3'd0}] <= dina[((1*B_DATA_WIDTH)-1):(B_DATA_WIDTH*0)];
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m_ram[{addra, 3'd1}] <= dina[((2*B_DATA_WIDTH)-1):(B_DATA_WIDTH*1)];
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m_ram[{addra, 3'd2}] <= dina[((3*B_DATA_WIDTH)-1):(B_DATA_WIDTH*2)];
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m_ram[{addra, 3'd3}] <= dina[((4*B_DATA_WIDTH)-1):(B_DATA_WIDTH*3)];
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m_ram[{addra, 3'd4}] <= dina[((5*B_DATA_WIDTH)-1):(B_DATA_WIDTH*4)];
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m_ram[{addra, 3'd5}] <= dina[((6*B_DATA_WIDTH)-1):(B_DATA_WIDTH*5)];
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m_ram[{addra, 3'd6}] <= dina[((7*B_DATA_WIDTH)-1):(B_DATA_WIDTH*6)];
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m_ram[{addra, 3'd7}] <= dina[((8*B_DATA_WIDTH)-1):(B_DATA_WIDTH*7)];
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end
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end
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end
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endgenerate
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// read interface options
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generate if ((MEM_IO_COMP == 1) || (MEM_RATIO == 1)) begin
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always @(posedge clkb) begin
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doutb <= m_ram[addrb];
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 2)) begin
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always @(posedge clkb) begin
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doutb <= {m_ram[{addrb, 1'd1}],
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m_ram[{addrb, 1'd0}]};
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 4)) begin
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always @(posedge clkb) begin
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doutb <= {m_ram[{addrb, 2'd3}],
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m_ram[{addrb, 2'd2}],
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m_ram[{addrb, 2'd1}],
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m_ram[{addrb, 2'd0}]};
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end
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end
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endgenerate
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generate if ((MEM_IO_COMP == 0) && (MEM_RATIO == 8)) begin
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always @(posedge clkb) begin
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doutb <= {m_ram[{addrb, 3'd7}],
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m_ram[{addrb, 3'd6}],
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m_ram[{addrb, 3'd5}],
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m_ram[{addrb, 3'd4}],
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m_ram[{addrb, 3'd3}],
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m_ram[{addrb, 3'd2}],
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m_ram[{addrb, 3'd1}],
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m_ram[{addrb, 3'd0}]};
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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