89 lines
2.2 KiB
Verilog
89 lines
2.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_rx_cgs #(
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parameter DATA_PATH_WIDTH = 4
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) (
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input clk,
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input reset,
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input [DATA_PATH_WIDTH-1:0] char_is_cgs,
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input [DATA_PATH_WIDTH-1:0] char_is_error,
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output ready,
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output [1:0] status_state
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);
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localparam CGS_STATE_INIT = 2'b00;
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localparam CGS_STATE_CHECK = 2'b01;
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localparam CGS_STATE_DATA = 2'b10;
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reg [1:0] state = CGS_STATE_INIT;
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reg rdy = 1'b0;
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reg [1:0] beat_error_count = 'h00;
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wire beat_is_cgs = &char_is_cgs;
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wire beat_has_error = |char_is_error;
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wire beat_is_all_error = &char_is_error;
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assign ready = rdy;
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assign status_state = state;
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always @(posedge clk) begin
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if (state == CGS_STATE_INIT) begin
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beat_error_count <= 'h00;
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end else begin
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if (beat_has_error == 1'b1) begin
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beat_error_count <= beat_error_count + 1'b1;
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end else begin
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beat_error_count <= 'h00;
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end
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= CGS_STATE_INIT;
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end else begin
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case (state)
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CGS_STATE_INIT: begin
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if (beat_is_cgs == 1'b1) begin
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state <= CGS_STATE_CHECK;
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end
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end
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CGS_STATE_CHECK: begin
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if (beat_has_error == 1'b1) begin
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if (beat_error_count == 'h3 ||
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beat_is_all_error == 1'b1) begin
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state <= CGS_STATE_INIT;
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end
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end else begin
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state <= CGS_STATE_DATA;
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end
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end
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CGS_STATE_DATA: begin
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if (beat_has_error == 1'b1) begin
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state <= CGS_STATE_CHECK;
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end
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end
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endcase
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end
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end
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always @(posedge clk) begin
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case (state)
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CGS_STATE_INIT: rdy <= 1'b0;
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CGS_STATE_DATA: rdy <= 1'b1;
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default: rdy <= rdy;
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endcase
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end
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endmodule
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