68 lines
3.4 KiB
Markdown
68 lines
3.4 KiB
Markdown
# ADRV9361Z7035 SDR SOM
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This folder contains the ADRV9361Z7035 SOM projects for each of the carrier boards.
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# Supported SOM & Carriers
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|Directory | Description |
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|---------------|----------------------------------------------------|
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|ccbob\_cmos | ADRV9361Z7035\-SOM (CMOS Mode) \+ ADRV1CRR\-BOB |
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|ccbob\_lvds | ADRV9361Z7035\-SOM (LVDS Mode) \+ ADRV1CRR\-BOB |
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|ccpackrf\_lvds | ADRV9361Z7035\-SOM (LVDS Mode) \+ ADRV1CRR\-PACKRF |
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|ccfmc\_lvds | ADRV9361Z7035\-SOM (LVDS Mode) \+ ADRV1CRR\-FMC |
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|ccpci\_lvds | ADRV9361Z7035\-SOM (LVDS Mode) \+ ADRV1CRR\-PCI |
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|ccusb\_lvds | ADRV9361Z7035\-SOM (LVDS Mode) \+ ADRV1CRR\-USB |
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## Board Design Files (Vivado IPI)
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|Directory/File | Description |
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|-----------------------------|----------------------------------------|
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|common/adrv9361z7035\_bd.tcl | ADRV9361Z7035\-SOM board design file. |
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|common/ccbob\_bd.tcl | carrier, break out board design file. |
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|common/ccpackrf\_bd.tcl | carrier, pack rf board design file. |
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|common/ccfmc\_bd.tcl | carrier, fmc board design file. |
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|common/ccpci\_bd.tcl | carrier, pci-e board design file. |
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|common/ccusb\_bd.tcl | carrier, usb board design file. |
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FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.
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## Board Constraint Files (pin-out & io-standard)
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|Directory/File | Description |
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|----------------------------------------|-------------------------------------------------|
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|common/adrv9361z7035\_constr.xdc | ADRV9361Z7035\-SOM base constraints file. |
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|common/adrv9361z7035\_constr\_cmos.xdc | ADRV9361Z7035\-SOM CMOS mode constraints file. |
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|common/adrv9361z7035\_constr\_lvds.xdc | ADRV9361Z7035\-SOM LVDS mode constraints file. |
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|common/ccbob\_constr.xdc | carrier, break out board constraints file. |
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|common/ccpackrf\_constr.xdc | carrier, packrf board constraints file. |
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|common/ccfmc\_constr.xdc | carrier, fmc board constraints file. |
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|common/ccpci\_constr.xdc | carrier, pci-e board constraints file. |
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|common/ccusb\_constr.xdc | carrier, usb board constraints file. |
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FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.
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## Building, Generating Bit Files (easy & efficient method)
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```
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[some-directory]> git clone -b dev git@github.com:analogdevicesinc/hdl.git
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[some-directory]> make -C hdl/projects/adrv9361z7035/ccbob_cmos
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```
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## Building, Generating Elf Files (easy & efficient method)
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```
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[some-directory]> git clone -b dev git@github.com:analogdevicesinc/no-OS.git
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[some-directory]> make -C no-OS/adrv9361z7035/ccbob_cmos
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```
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## Running, a quick test (easy & efficient method)
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```
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[some-directory]> make -C no-OS/adrv9361z7035/ccbob_cmos run
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```
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# ADRV9361Z7035 HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/ADRV9361-Z7035)
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* Parts : [RF Agile Transceiver](https://www.analog.com/ad9361)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361
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