228 lines
6.8 KiB
Verilog
Executable File
228 lines
6.8 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modificat
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad3552r_channel #(
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parameter CHANNEL_ID = 32'h0,
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parameter DDS_DISABLE = 0,
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parameter DDS_TYPE = 1,
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parameter DDS_CORDIC_DW = 16,
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parameter DDS_CORDIC_PHASE_DW = 16
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) (
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// dac interface
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input dac_clk,
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input dac_rst,
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output dac_data_valid,
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output [15:0] dac_data,
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// input sources
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input [15:0] dma_data,
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input [15:0] adc_data,
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input valid_in_adc,
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input valid_in_dma,
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input dac_data_ready,
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// processor interface
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input dac_data_sync,
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input dac_dfmt_type,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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// internal signals
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wire [15:0] formatted_dma_data;
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wire [15:0] formatted_adc_data;
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wire [ 3:0] dac_data_sel_s;
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wire [15:0] dac_dds_data_s;
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wire [15:0] dac_dds_scale_1_s;
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_scale_2_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_pat_data_1_s;
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wire [15:0] dac_pat_data_2_s;
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reg [15:0] ramp_pattern = 16'h0000;
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reg ramp_valid = 1'b0;
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reg [15:0] dac_data_int;
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reg dac_data_valid_int;
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assign dac_data = dac_data_int;
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assign dac_data_valid = dac_data_valid_int;
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assign formatted_dma_data [15] = dac_dfmt_type ^ dma_data[15];
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assign formatted_dma_data [14:0] = dma_data[14:0];
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assign formatted_adc_data [15] = dac_dfmt_type ^ adc_data[15];
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assign formatted_adc_data [14:0] = adc_data[14:0];
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always @ (*) begin
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case(dac_data_sel_s)
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4'h0 :
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begin
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dac_data_int = dac_dds_data_s;
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dac_data_valid_int = 1'b1;
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end
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4'h2 :
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begin
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dac_data_int = formatted_dma_data;
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dac_data_valid_int = valid_in_dma;
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end
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4'h3 :
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begin
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dac_data_int = 16'b0;
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dac_data_valid_int = 1'b1;
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end
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4'h8 :
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begin
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dac_data_int = formatted_adc_data;
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dac_data_valid_int = valid_in_adc;
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end
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4'hb :
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begin
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dac_data_int = ramp_pattern;
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dac_data_valid_int = ramp_valid;
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end
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default :
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begin
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dac_data_int = 16'b0;
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dac_data_valid_int = 1'b1;
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end
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endcase
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end
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// ramp generator
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always @(posedge dac_clk) begin
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ramp_valid <= 1'b1;
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if(dac_data_ready == 1'b1) begin
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ramp_pattern <= ramp_pattern + 1'b1;
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end else begin
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ramp_pattern <= ramp_pattern;
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end
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if(ramp_pattern == 16'hffff || dac_rst == 1'b1) begin
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ramp_pattern <= 16'h0;
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end
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end
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ad_dds #(
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.DISABLE (DDS_DISABLE),
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.DDS_DW (16),
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.PHASE_DW (16),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (DDS_CORDIC_DW),
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.CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
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.CLK_RATIO (1)
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) i_dds (
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.clk (dac_clk),
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.dac_dds_format (dac_dfmt_type),
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.dac_data_sync (dac_data_sync),
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.dac_valid (dac_data_ready),
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.tone_1_scale (dac_dds_scale_1_s),
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.tone_2_scale (dac_dds_scale_2_s),
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.tone_1_init_offset (dac_dds_init_1_s),
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.tone_2_init_offset (dac_dds_init_2_s),
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.tone_1_freq_word (dac_dds_incr_1_s),
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.tone_2_freq_word (dac_dds_incr_2_s),
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.dac_dds_data (dac_dds_data_s));
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// single channel processor
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up_dac_channel #(
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.CHANNEL_ID(CHANNEL_ID),
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.COMMON_ID(6'h01)
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) dac_channel (
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.dac_clk(dac_clk),
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.dac_rst(dac_rst),
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.dac_dds_scale_1(dac_dds_scale_1_s),
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.dac_dds_init_1(dac_dds_init_1_s),
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.dac_dds_incr_1(dac_dds_incr_1_s),
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.dac_dds_scale_2(dac_dds_scale_2_s),
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.dac_dds_init_2(dac_dds_init_2_s),
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.dac_dds_incr_2(dac_dds_incr_2_s),
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.dac_pat_data_1(dac_pat_data_1_s),
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.dac_pat_data_2(dac_pat_data_2_s),
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.dac_data_sel(dac_data_sel_s),
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.dac_mask_enable(),
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.dac_iq_mode(),
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.dac_iqcor_enb(),
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.dac_iqcor_coeff_1(),
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.dac_iqcor_coeff_2(),
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.dac_src_chan_sel(),
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.up_usr_datatype_be(),
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.up_usr_datatype_signed(),
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.up_usr_datatype_shift(),
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.up_usr_datatype_total_bits(),
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.up_usr_datatype_bits(),
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.up_usr_interpolation_m(),
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.up_usr_interpolation_n(),
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.dac_usr_datatype_be(1'd0),
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.dac_usr_datatype_signed(1'd1),
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.dac_usr_datatype_shift(8'd0),
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.dac_usr_datatype_total_bits(8'd16),
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.dac_usr_datatype_bits(8'd16),
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.dac_usr_interpolation_m(16'd1),
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.dac_usr_interpolation_n(16'd1),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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endmodule
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