304 lines
11 KiB
Plaintext
304 lines
11 KiB
Plaintext
###############################################################################
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## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier *cdc_sync_stage2_reg*]
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# i_wr_transfer constraints
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# .async_req_src(0),
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# .async_src_dest(1),
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# .async_dest_req(1),
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set req_clk [get_clocks -of_objects [get_ports s_axis_aclk]]
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set src_clk [get_clocks -of_objects [get_ports s_axis_aclk]]
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set dest_clk [get_clocks -of_objects [get_ports m_axi_aclk]]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_sync_req_response_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_false_path -quiet \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_sync_status_dest* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_sync_control_dest* && IS_SEQUENTIAL}]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_response_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_response_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_response_fifo* && IS_SEQUENTIAL}] \
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-to $req_clk \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_sync_dest_request_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_store_and_forward/i_dest_sync_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_store_and_forward/i_src_sync_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-through [get_cells -quiet -hier \
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-filter {IS_SEQUENTIAL && NAME =~ *i_wr_transfer*i_store_and_forward/burst_len_mem_reg*}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_wr_transfer*i_dest_req_fifo* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-through [get_cells -quiet -hier DP \
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-filter {NAME =~ *i_wr_transfer*i_request_arb/eot_mem_dest_reg*}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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# i_rd_transfer constraints
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# .async_req_src(1),
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# .async_src_dest(1),
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# .async_dest_req(0),
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set req_clk [get_clocks -of_objects [get_ports m_axis_aclk]]
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set src_clk [get_clocks -of_objects [get_ports m_axi_aclk]]
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set dest_clk [get_clocks -of_objects [get_ports m_axis_aclk]]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_sync_src_request_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_false_path -quiet \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_sync_status_src* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_sync_control_src* && IS_SEQUENTIAL}]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_req_fifo* && IS_SEQUENTIAL}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-through [get_cells -quiet -hier DP \
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-filter {NAME =~ *i_rd_transfer*i_request_arb/eot_mem_src_reg*}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo* && IS_SEQUENTIAL}] \
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-to $req_clk \
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[get_property -min PERIOD $req_clk]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*sync_rewind/i_sync_out* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*sync_rewind/i_sync_in* && IS_SEQUENTIAL}]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_sync_dest_request_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_store_and_forward/i_dest_sync_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_store_and_forward/i_src_sync_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-through [get_cells -quiet -hier \
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-filter {IS_SEQUENTIAL && NAME =~ *i_rd_transfer*i_store_and_forward/burst_len_mem_reg*}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_rd_transfer*i_dest_req_fifo* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-through [get_cells -quiet -hier DP \
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-filter {NAME =~ *i_rd_transfer*i_request_arb/eot_mem_dest_reg*}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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#
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# Common to both dmas
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#
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# Reset signals
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set_false_path -quiet \
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-from [get_cells -quiet -hier *do_reset_reg* \
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-filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \
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-to [get_pins -quiet -hier *reset_async_reg*/PRE]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *reset_async_reg[0] \
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-filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hier *reset_async_reg[3]* \
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-filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *reset_async_reg[0] \
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-filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \
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-to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \
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-filter {NAME =~ *i_reset_manager*}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *reset_sync_reg[0] \
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-filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \
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-to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \
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-filter {NAME =~ *i_reset_manager*}]
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set_property -dict { \
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SHREG_EXTRACT NO \
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ASYNC_REG TRUE \
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} [get_cells -quiet -hier *reset_async_reg*]
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set_property -dict { \
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SHREG_EXTRACT NO \
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ASYNC_REG TRUE \
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} [get_cells -quiet -hier *reset_sync_reg*]
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