126 lines
4.4 KiB
Verilog
126 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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//------------------------------------------------------------------------------
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//----------- Module Declaration -----------------------------------------------
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//------------------------------------------------------------------------------
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module clk_div
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(
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// Clock and Reset signals
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input clk_i,
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input reset_n_i,
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// Clock divider
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input new_div_i,
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input [31:0] div_i,
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input new_phase_inc_i,
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input [31:0] phase_inc_i,
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// Divided clock output
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output reg reg_update_rdy_o,
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output clk_o,
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output [31:0] phase_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [31:0] div;
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reg [31:0] div_cnt;
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reg [31:0] phase;
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reg [31:0] phase_inc;
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reg clk_div;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign clk_o = clk_div;
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assign phase_o = phase;
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// Register update logic
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always @(posedge clk_i)
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begin
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if(reset_n_i == 1'b0)
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begin
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div <= 'd0;
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phase_inc <= 'd0;
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reg_update_rdy_o <= 1'b0;
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end
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else
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begin
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if(new_div_i == 1'b1)
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begin
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div <= div_i;
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end
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if(new_phase_inc_i == 1'b1)
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begin
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phase_inc <= phase_inc_i;
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end
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reg_update_rdy_o <= new_div_i | new_phase_inc_i;
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end
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end
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// Clock division logic
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always @(posedge clk_i)
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begin
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if(reset_n_i == 1'b0)
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begin
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clk_div <= 'd1;
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phase <= 'd0;
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end
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else
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begin
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if(div_cnt < div)
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begin
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div_cnt <= div_cnt + 'd1;
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end
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else
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begin
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div_cnt <= 'd1;
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//clk_div <= ~clk_div;
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end
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phase <= phase + phase_inc;
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clk_div <= phase[31];
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end
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end
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endmodule
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