Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint ... According to data sheets the EMIO SPI controller maximum frequency is just 25MHz. Constrain the SPI clock accordingly.		2019-08-09 16:39:56 +03:00
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Makefile	Regenerate project Makefiles using the new shared Makefile includes	2018-04-11 15:09:54 +03:00
system_bd.tcl	pluto: Fix the adc/dac dma mapping to ps7 S_AXI_HP1/S_AXI_HP2	2019-05-27 17:20:44 +03:00
system_constr.xdc	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00
system_project.tcl	project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl	2019-06-29 06:53:51 +03:00
system_top.v	all/system_top.v: loopback gpio lines	2018-10-04 14:19:37 +03:00