294 lines
8.4 KiB
Verilog
294 lines
8.4 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
|
//
|
|
// In this HDL repository, there are many different and unique modules, consisting
|
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
|
// developed independently, and may be accompanied by separate and unique license
|
|
// terms.
|
|
//
|
|
// The user should read each of these license terms, and understand the
|
|
// freedoms and responsibilities that he or she has by using this source/core.
|
|
//
|
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
// A PARTICULAR PURPOSE.
|
|
//
|
|
// Redistribution and use of source or resulting binaries, with or without modification
|
|
// of this file, are permitted under one of the following two license terms:
|
|
//
|
|
// 1. The GNU General Public License version 2 as published by the
|
|
// Free Software Foundation, which can be found in the top level directory
|
|
// of this repository (LICENSE_GPL2), and also online at:
|
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
|
//
|
|
// OR
|
|
//
|
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
|
// This will allow to generate bit files and not release the source code,
|
|
// as long as it attaches to an ADI device.
|
|
//
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
module system_top #(
|
|
parameter TX_JESD_L = 4,
|
|
parameter TX_NUM_LINKS = 1,
|
|
parameter RX_JESD_L = 4,
|
|
parameter RX_NUM_LINKS = 1
|
|
) (
|
|
input sys_clk_n,
|
|
input sys_clk_p,
|
|
output ddr4_act_n,
|
|
output [16:0] ddr4_adr,
|
|
output [1:0] ddr4_ba,
|
|
output [1:0] ddr4_bg,
|
|
output ddr4_ck_c,
|
|
output ddr4_ck_t,
|
|
output ddr4_cke,
|
|
output ddr4_cs_n,
|
|
inout [7:0] ddr4_dm_n,
|
|
inout [63:0] ddr4_dq,
|
|
inout [7:0] ddr4_dqs_c,
|
|
inout [7:0] ddr4_dqs_t,
|
|
output ddr4_odt,
|
|
output ddr4_reset_n,
|
|
// GPIOs
|
|
output [3:0] gpio_led,
|
|
input [3:0] gpio_dip_sw,
|
|
input [1:0] gpio_pb,
|
|
|
|
// FMC HPC IOs
|
|
input [1:0] agc0,
|
|
input [1:0] agc1,
|
|
input [1:0] agc2,
|
|
input [1:0] agc3,
|
|
input clkin6_n,
|
|
input clkin6_p,
|
|
input clkin10_n,
|
|
input clkin10_p,
|
|
input fpga_refclk_in_n,
|
|
input fpga_refclk_in_p,
|
|
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
|
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
|
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
|
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
|
input [TX_NUM_LINKS-1:0] fpga_syncin_n,
|
|
input [TX_NUM_LINKS-1:0] fpga_syncin_p,
|
|
output [RX_NUM_LINKS-1:0] fpga_syncout_n,
|
|
output [RX_NUM_LINKS-1:0] fpga_syncout_p,
|
|
inout [10:0] gpio,
|
|
inout hmc_gpio1,
|
|
output hmc_sync,
|
|
input [1:0] irqb,
|
|
output rstb,
|
|
output [1:0] rxen,
|
|
output spi0_csb,
|
|
input spi0_miso,
|
|
output spi0_mosi,
|
|
output spi0_sclk,
|
|
output spi1_csb,
|
|
output spi1_sclk,
|
|
inout spi1_sdio,
|
|
input sysref2_n,
|
|
input sysref2_p,
|
|
output [1:0] txen
|
|
|
|
);
|
|
|
|
// internal signals
|
|
|
|
wire [95:0] gpio_i;
|
|
wire [95:0] gpio_o;
|
|
wire [95:0] gpio_t;
|
|
|
|
wire [ 2:0] spi0_csn;
|
|
|
|
wire [ 2:0] spi1_csn;
|
|
wire spi1_mosi;
|
|
wire spi1_miso;
|
|
|
|
wire sysref;
|
|
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
|
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
|
|
|
wire [7:0] rx_data_p_loc;
|
|
wire [7:0] rx_data_n_loc;
|
|
wire [7:0] tx_data_p_loc;
|
|
wire [7:0] tx_data_n_loc;
|
|
|
|
wire clkin6;
|
|
wire clkin10;
|
|
wire tx_device_clk;
|
|
wire rx_device_clk;
|
|
|
|
// instantiations
|
|
|
|
IBUFDS i_ibufds_sysref (
|
|
.I (sysref2_p),
|
|
.IB (sysref2_n),
|
|
.O (sysref));
|
|
|
|
IBUFDS i_ibufds_tx_device_clk (
|
|
.I (clkin6_p),
|
|
.IB (clkin6_n),
|
|
.O (clkin6));
|
|
|
|
IBUFDS i_ibufds_rx_device_clk (
|
|
.I (clkin10_p),
|
|
.IB (clkin10_n),
|
|
.O (clkin10));
|
|
|
|
genvar i;
|
|
generate
|
|
for(i=0;i<TX_NUM_LINKS;i=i+1) begin : g_tx_buffers
|
|
IBUFDS i_ibufds_syncin (
|
|
.I (fpga_syncin_p[i]),
|
|
.IB (fpga_syncin_n[i]),
|
|
.O (tx_syncin[i]));
|
|
end
|
|
|
|
for(i=0;i<RX_NUM_LINKS;i=i+1) begin : g_rx_buffers
|
|
OBUFDS i_obufds_syncout (
|
|
.I (rx_syncout[i]),
|
|
.O (fpga_syncout_p[i]),
|
|
.OB (fpga_syncout_n[i]));
|
|
end
|
|
endgenerate
|
|
|
|
BUFG i_tx_device_clk (
|
|
.I (clkin6),
|
|
.O (tx_device_clk)
|
|
);
|
|
|
|
BUFG i_rx_device_clk (
|
|
.I (clkin10),
|
|
.O (rx_device_clk)
|
|
);
|
|
// spi
|
|
|
|
assign spi0_csb = spi0_csn[0];
|
|
assign spi1_csb = spi1_csn[0];
|
|
|
|
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
|
|
.spi_csn (spi1_csn[0]),
|
|
.spi_clk (spi1_sclk),
|
|
.spi_mosi (spi1_mosi),
|
|
.spi_miso (spi1_miso),
|
|
.spi_sdio (spi1_sdio),
|
|
.spi_dir ());
|
|
|
|
// gpios
|
|
|
|
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
|
|
.dio_t (gpio_t[43:32]),
|
|
.dio_i (gpio_o[43:32]),
|
|
.dio_o (gpio_i[43:32]),
|
|
.dio_p ({hmc_gpio1, // 43
|
|
gpio[10:0]})); // 42-32
|
|
|
|
assign gpio_i[44] = agc0[0];
|
|
assign gpio_i[45] = agc0[1];
|
|
assign gpio_i[46] = agc1[0];
|
|
assign gpio_i[47] = agc1[1];
|
|
assign gpio_i[48] = agc2[0];
|
|
assign gpio_i[49] = agc2[1];
|
|
assign gpio_i[50] = agc3[0];
|
|
assign gpio_i[51] = agc3[1];
|
|
assign gpio_i[52] = irqb[0];
|
|
assign gpio_i[53] = irqb[1];
|
|
|
|
assign hmc_sync = gpio_o[54];
|
|
assign rstb = gpio_o[55];
|
|
assign rxen[0] = gpio_o[56];
|
|
assign rxen[1] = gpio_o[57];
|
|
assign txen[0] = gpio_o[58];
|
|
assign txen[1] = gpio_o[59];
|
|
|
|
/* Board GPIOS. Buttons, LEDs, etc... */
|
|
assign gpio_led = gpio_o[3:0];
|
|
assign gpio_i[3:0] = gpio_o[3:0];
|
|
assign gpio_i[7: 4] = gpio_dip_sw;
|
|
assign gpio_i[9: 8] = gpio_pb;
|
|
|
|
// Unused GPIOs
|
|
assign gpio_i[94:54] = gpio_o[94:54];
|
|
assign gpio_i[31:10] = gpio_o[31:10];
|
|
|
|
reg ext_pll_lock,ext_pll_lock_d;
|
|
|
|
always @(posedge tx_device_clk) begin
|
|
ext_pll_lock <= gpio_i[43];
|
|
ext_pll_lock_d <= ext_pll_lock;
|
|
end
|
|
|
|
assign gt_reset = ext_pll_lock & ~ext_pll_lock_d;
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.gpio0_i (gpio_i[31:0]),
|
|
.gpio0_o (gpio_o[31:0]),
|
|
.gpio0_t (gpio_t[31:0]),
|
|
.gpio1_i (gpio_i[63:32]),
|
|
.gpio1_o (gpio_o[63:32]),
|
|
.gpio1_t (gpio_t[63:32]),
|
|
.gpio2_i (gpio_i[95:64]),
|
|
.gpio2_o (gpio_o[95:64]),
|
|
.gpio2_t (gpio_t[95:64]),
|
|
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
|
|
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
|
|
.ddr4_dimm1_act_n (ddr4_act_n),
|
|
.ddr4_dimm1_adr (ddr4_adr),
|
|
.ddr4_dimm1_ba (ddr4_ba),
|
|
.ddr4_dimm1_bg (ddr4_bg),
|
|
.ddr4_dimm1_ck_c (ddr4_ck_c),
|
|
.ddr4_dimm1_ck_t (ddr4_ck_t),
|
|
.ddr4_dimm1_cke (ddr4_cke),
|
|
.ddr4_dimm1_cs_n (ddr4_cs_n),
|
|
.ddr4_dimm1_dm_n (ddr4_dm_n),
|
|
.ddr4_dimm1_dq (ddr4_dq),
|
|
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
|
|
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
|
|
.ddr4_dimm1_odt (ddr4_odt),
|
|
.ddr4_dimm1_reset_n (ddr4_reset_n),
|
|
.spi0_csn (spi0_csn),
|
|
.spi0_miso (spi0_miso),
|
|
.spi0_mosi (spi0_mosi),
|
|
.spi0_sclk (spi0_sclk),
|
|
.spi1_csn (spi1_csn),
|
|
.spi1_miso (spi1_miso),
|
|
.spi1_mosi (spi1_mosi),
|
|
.spi1_sclk (spi1_sclk),
|
|
// FMC HPC
|
|
// TODO: Max 4 lanes
|
|
.GT_Serial_0_gtx_p (tx_data_p_loc[3:0]),
|
|
.GT_Serial_0_gtx_n (tx_data_n_loc[3:0]),
|
|
.GT_Serial_0_grx_p (rx_data_p_loc[3:0]),
|
|
.GT_Serial_0_grx_n (rx_data_n_loc[3:0]),
|
|
|
|
.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_p(fpga_refclk_in_p),
|
|
.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_n(fpga_refclk_in_n),
|
|
|
|
.rx_device_clk (rx_device_clk),
|
|
.tx_device_clk (tx_device_clk),
|
|
.rx_sync_0 (rx_syncout),
|
|
.tx_sync_0 (tx_syncin),
|
|
.rx_sysref_0 (sysref),
|
|
.tx_sysref_0 (sysref),
|
|
.gt_reset (gt_reset)
|
|
);
|
|
|
|
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
|
|
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
|
|
|
|
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
|
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|