112 lines
4.1 KiB
Verilog
112 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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/*
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* Helper module for synchronizing a counter from one clock domain to another
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* using gray code. To work correctly the counter must not change its value by
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* more than one in one clock cycle in the source domain. I.e. the value may
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* change by either -1, 0 or +1.
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*/
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module sync_gray (
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input in_clk,
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input in_resetn,
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input [DATA_WIDTH-1:0] in_count,
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input out_resetn,
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input out_clk,
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output [DATA_WIDTH-1:0] out_count
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);
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// Bit-width of the counter
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parameter DATA_WIDTH = 1;
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// Whether the input and output clock are asynchronous, if set to 0 the
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// synchronizer will be bypassed and out_count will be in_count.
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parameter ASYNC_CLK = 1;
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reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
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reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
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reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
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reg [DATA_WIDTH-1:0] out_count_m = 'h0;
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function [DATA_WIDTH-1:0] g2b;
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input [DATA_WIDTH-1:0] g;
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reg [DATA_WIDTH-1:0] b;
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integer i;
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begin
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b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
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for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
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b[i] = b[i + 1] ^ g[i];
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g2b = b;
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end
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endfunction
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function [DATA_WIDTH-1:0] b2g;
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input [DATA_WIDTH-1:0] b;
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reg [DATA_WIDTH-1:0] g;
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integer i;
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begin
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g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
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for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
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g[i] = b[i + 1] ^ b[i];
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b2g = g;
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end
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endfunction
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always @(posedge in_clk) begin
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if (in_resetn == 1'b0) begin
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cdc_sync_stage0 <= 'h00;
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end else begin
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cdc_sync_stage0 <= b2g(in_count);
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end
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end
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always @(posedge out_clk) begin
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if (out_resetn == 1'b0) begin
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cdc_sync_stage1 <= 'h00;
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cdc_sync_stage2 <= 'h00;
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out_count_m <= 'h00;
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end else begin
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cdc_sync_stage1 <= cdc_sync_stage0;
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cdc_sync_stage2 <= cdc_sync_stage1;
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out_count_m <= g2b(cdc_sync_stage2);
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end
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end
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assign out_count = ASYNC_CLK ? out_count_m : in_count;
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endmodule
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