pluto_hdl_adi/library/axi_dmac
Lars-Peter Clausen 374c49ff48 axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.

Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.

In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
..
bd axi_dmac: post_propagate(): Handle mappings with multiple address segments 2017-04-19 13:47:02 +02:00
2d_transfer.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
Makefile Create CDC helper library 2017-05-23 11:16:07 +02:00
address_generator.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
axi_dmac.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
axi_dmac_constr.sdc axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them 2015-07-23 17:01:02 +03:00
axi_dmac_constr.ttcl axi_dmac: Make debug register optional 2017-04-18 12:17:39 +02:00
axi_dmac_hw.tcl axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains 2017-07-24 16:06:37 +02:00
axi_dmac_ip.tcl Create CDC helper library 2017-05-23 11:16:07 +02:00
axi_register_slice.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
data_mover.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
dest_axi_mm.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
dest_axi_stream.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
dest_fifo_inf.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
inc_id.h axi_dmac: Parameter changes 2015-08-20 16:06:26 +03:00
request_arb.v axi_dmac: request_arb: Add missing req_gen_{valid,ready} signal declaration 2017-07-17 17:13:02 +02:00
request_generator.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
resp.h Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
response_generator.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
response_handler.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
splitter.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
src_axi_mm.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
src_axi_stream.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
src_fifo_inf.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00