9 lines
13 KiB
Plaintext
9 lines
13 KiB
Plaintext
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Record=SheetSymbol|SourceDocument=Top.SchDoc|Designator=U_uP_KR_OB|SchDesignator=U_uP_KR_OB|FileName=uP_KR_OB.OpenBus|SymbolType=Normal|RawFileName=uP_KR_OB.OpenBus|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SubProject|ProjectPath=Embedded.PrjEmb
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Record=TopLevelDocument|FileName=Top.SchDoc
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Record=NEXUS_CORE|ComponentDesignator=TSK3000A_1|BaseComponentDesignator=TSK3000A_1|DocumentName=uP_KR_OB.OpenBus|LibraryReference=TSK3000A|NexusDeviceId=TSK3000A|SubProjectPath=Embedded.PrjEmb|NEXUS_JTAG_INDEX=0|ComponentUniqueID=STOVHICG|Description=OpenBus Component|ChildModel1=TSK3000A_MCU|ChildModel2=TSK3000A_MDU|ChildModel3=TSK3000A_OCDS|ChildModel4=TSK3000A_Shift_Barrel|ChildModel5=TSK3000A_Shift_Sequential|ChildModel6=Mult_32x32|ChildModel7=m33x33|Comment= |Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0140 FPGA Processor Resource Usage.pdf#page=22|ComponentLink2Description=Embedded &Tools Guide|ComponentLink2URL=GU0111 Using the TSK3000 Embedded Tools.pdf|ComponentLink3Description=Embedded T&echnical References|ComponentLink3URL=TR0109 TSK3000 Embedded Tools Reference.pdf|ConfigurationParameters={}Version[1.0]{}Option_Processor[0]{}Option_Memory[2]{}Option_MDU[0]{}Option_OCDS[0]{}Option_Shifter[0]{}Option_InterruptCount[32]{}Option_DebugWhenReset[0]{}|ConfiguratorName=FPGA_MCU32|ExportedInterrupts=0000000000000000,FFFFFFFF,FFFFFFFF|Footprint= |HelpURL=CR0121 TSK3000A 32 bit RISC Processor.pdf|LastRevisionNo=1.00.00|Library Name= |Library Reference=TSK3000A|Memory_Configuration=Record[AUTOIMPORT]{}AutoImport_Memory[True]{}AutoImport_Peripherals[True]{n}Record[NEXUS_CORE]{}ComponentDesignator[TSK3000A_1]{}Memory_Depth[4096]{}Memory_UsageType[rom]{}ProgramDownloadAddress[0x0]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[NEXUS_CORE]{}ComponentDesignator[BlockMem]{}Memory_Depth[0x2000]{}Memory_UsageType[ram]{}ProgramDownloadAddress[0x1000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_2]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PHYSICAL_MEMORY]{}ComponentDesignator[TSK3000A_1]{}Memory_Depth[4096]{}Memory_UsageType[rom]{}ProgramDownloadAddress[0x0]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PHYSICAL_MEMORY]{}ComponentDesignator[BlockMem]{}Memory_Depth[0x2000]{}Memory_UsageType[ram]{}ProgramDownloadAddress[0x1000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_2]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[CODE_EXPORT]{}ExportType[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_4]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_7]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF020000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_0]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF030000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_2]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF040000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Mem
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Record=NEXUS_CORE|ComponentDesignator=U1|BaseComponentDesignator=U1|DocumentName=Top.SchDoc|LibraryReference=RAMSEB_32x2K|NexusDeviceId=RAMSEB_32x2K|SubProjectPath= |NEXUS_JTAG_INDEX=0|ComponentUniqueID=SEHJNSFO|Description=Single Port RAM, Enable, Byte Write Enable|Comment=RAMSEB_32x2K|Component Kind=Standard|Footprint= |Library Name=FPGA Memories.IntLib|Library Reference=RAMSEB_32x2K|Memory_ByteWrites=True|Memory_ClockEdge=Rising|Memory_ContentFile= |Memory_Depth=2048|Memory_EnablePin=True|Memory_Type=RAM_SinglePortBlock|Memory_Width=32|Nexus_Core=Memory_Program|PCB3D= |Published=11/10/2004|Publisher=Altium Hobart Technology Center|Signal Integrity= |Simulation=
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Record=NEXUS_CORE_COMPONENT|BaseComponentDesignator=TSK3000A_1|DocumentName=uP_KR_OB.OpenBus|LibraryReference=TSK3000A|SubProjectPath=Embedded.PrjEmb|Configuration= |Description=OpenBus Component|NexusDeviceId=TSK3000A|SubPartUniqueId1=STOVHICG|SubPartDocPath1=uP_KR_OB.OpenBus|ChildModel1=TSK3000A_MCU|ChildModel2=TSK3000A_MDU|ChildModel3=TSK3000A_OCDS|ChildModel4=TSK3000A_Shift_Barrel|ChildModel5=TSK3000A_Shift_Sequential|ChildModel6=Mult_32x32|ChildModel7=m33x33|Comment=*|Component Kind=Standard|ComponentLink1Description=Core &Resource Usage|ComponentLink1URL=CR0140 FPGA Processor Resource Usage.pdf#page=22|ComponentLink2Description=Embedded &Tools Guide|ComponentLink2URL=GU0111 Using the TSK3000 Embedded Tools.pdf|ComponentLink3Description=Embedded T&echnical References|ComponentLink3URL=TR0109 TSK3000 Embedded Tools Reference.pdf|ConfigurationParameters={}Version[1.0]{}Option_Processor[0]{}Option_Memory[2]{}Option_MDU[0]{}Option_OCDS[0]{}Option_Shifter[0]{}Option_InterruptCount[32]{}Option_DebugWhenReset[0]{}|ConfiguratorName=FPGA_MCU32|ExportedInterrupts=0000000000000000,FFFFFFFF,FFFFFFFF|Footprint= |HelpURL=CR0121 TSK3000A 32 bit RISC Processor.pdf|LastRevisionNo=1.00.00|Library Name= |Library Reference=TSK3000A|Memory_Configuration=Record[AUTOIMPORT]{}AutoImport_Memory[True]{}AutoImport_Peripherals[True]{n}Record[NEXUS_CORE]{}ComponentDesignator[TSK3000A_1]{}Memory_Depth[4096]{}Memory_UsageType[rom]{}ProgramDownloadAddress[0x0]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[NEXUS_CORE]{}ComponentDesignator[BlockMem]{}Memory_Depth[0x2000]{}Memory_UsageType[ram]{}ProgramDownloadAddress[0x1000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_2]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PHYSICAL_MEMORY]{}ComponentDesignator[TSK3000A_1]{}Memory_Depth[4096]{}Memory_UsageType[rom]{}ProgramDownloadAddress[0x0]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PHYSICAL_MEMORY]{}ComponentDesignator[BlockMem]{}Memory_Depth[0x2000]{}Memory_UsageType[ram]{}ProgramDownloadAddress[0x1000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_2]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[CODE_EXPORT]{}ExportType[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_4]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF000000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_7]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF020000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_0]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF030000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPattern[]{}Memory_IncludeDependencies[False]{}Memory_ByLoadAddress[False]{}Memory_Interrupts[]{n}Record[PERIPHERAL]{}ComponentDesignator[PWM_2]{}Memory_Depth[0x0004]{}Memory_UsageType[peripheral]{}ProgramDownloadAddress[0xFF040000]{}Memory_BusType[TSK3000:addr_bus]{}Memory_Mau[8]{}Memory_MatchedComponent[]{}Memory_Description[WB_INTERCON_1]{}Memory_FillBitPatter
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Record=NEXUS_CORE_COMPONENT|BaseComponentDesignator=U1|DocumentName=Top.SchDoc|LibraryReference=RAMSEB_32x2K|SubProjectPath= |Configuration= |Description=Single Port RAM, Enable, Byte Write Enable|NexusDeviceId=RAMSEB_32x2K|SubPartUniqueId1=SEHJNSFO|SubPartDocPath1=Top.SchDoc|Comment=RAMSEB_32x2K|Component Kind=Standard|Footprint= |Library Name=FPGA Memories.IntLib|Library Reference=RAMSEB_32x2K|Memory_ByteWrites=True|Memory_ClockEdge=Rising|Memory_ContentFile= |Memory_Depth=2048|Memory_EnablePin=True|Memory_Type=RAM_SinglePortBlock|Memory_Width=32|Nexus_Core=Memory_Program|PCB3D= |Published=11/10/2004|Publisher=Altium Hobart Technology Center|Signal Integrity= |Simulation=
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Record=Configuration|Name=NB2DSK01_08_DB30_06|DeviceName=XC3S1500-4FG676C
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