24 lines
1.2 KiB
Plaintext
24 lines
1.2 KiB
Plaintext
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;-------------------------------------------------------------------------------
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;Constraints File
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; Device : Any
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; Board : Nanboard 2
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; Project : SMS.PrjFpg
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;
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; Created 13-Nov-2008
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;; Altium Limited
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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Record=FileHeader | Id=DXP Constraints v1.0
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;-------------------------------------------------------------------------------
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;-------------------------------------------------------------------------------
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Record=Constraint | TargetKind=Port | TargetId=CLK_REF | FPGA_CLOCK=TRUE
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Record=Constraint | TargetKind=Port | TargetId=CLK_REF | FPGA_CLOCK_FREQUENCY=20 Mhz
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Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=TRUE
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Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50 Mhz
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Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=TRUE
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Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK_FREQUENCY=1 Mhz
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;-------------------------------------------------------------------------------
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