python-schdoc/tests/altium_crap/Circuit Sim/Analog Relay/Out/Analog Relay.nsx

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Analog Relay
*SPICE Netlist generated by Advanced Sim server on 11/06/2002 4:10:56 PM
*Schematic Netlist:
R1 OUT VCC 1k
R2 P1 0 500
R3 P2 0 1k
XRLY1 OUT P2 P1 IN 0 12VSPDT
V1 IN 0 DC 0 PULSE(0 12 0 1m 1m 4m 10m 0) AC 1 0
Vcc VCC 0 +12V
.SAVE 0 IN OUT P1 P2 VCC V1#branch Vcc#branch @V1[z] @Vcc[z] @R1[i] @R2[i] @R3[i]
.SAVE @R1[p] @R2[p] @R3[p] @V1[p] @Vcc[p]
*PLOT TRAN -1 1 A=IN A=OUT
*PLOT OP -1 1 A=IN A=OUT
*Selected Circuit Analyses:
.TRAN 0.0002 0.05 0 0.0002
.OP
*Models and Subcircuit:
.SUBCKT 12VSPDT 1 2 3 4 5
L1 4 6 5E-3
L2 5 7 5E-3
R1 6 7 1E+3
BNO 8 0 V=9.6E+0-ABS(V(6,7))
SW1 2 1 8 0 SWNC ON
BNC 9 0 V=ABS(V(6,7))
SW2 3 1 9 0 SWNO OFF
.MODEL SWNC SW(VT=1E-1 RON=1E-3 )
.MODEL SWNO SW(VT=9.408E+0 RON=1E-3 )
.ENDS SPDTRELAY
.END