python-schdoc/tests/altium_crap/Circuit Sim/Common Source JFET Amplifier/Out/Common Source JFET Amplifie...

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Common Source JFET Amplifier
*SPICE Netlist generated by Advanced Sim server on 11/06/2002 5:09:11 PM
*Schematic Netlist:
C1 IN G 1uF
C2 D OUT 1uF
J1 D G S 2N4393
R1 VCC D 2.5k
R2 G 0 1meg
R3 S 0 500
R4 OUT 0 1meg
V1 IN 0 DC 0V SIN(0 20m 1k 0 0) AC 1V 0V
V2 VCC 0 25V
.SAVE 0 D G IN OUT S VCC V1#branch V2#branch @V1[z] @V2[z] @C1[i] @C2[i] @J1[id]
.SAVE @J1[ig] @J1[is] @R1[i] @R2[i] @R3[i] @R4[i] @C1[p] @C2[p] @J1[p] @R1[p] @R2[p]
.SAVE @R3[p] @R4[p] @V1[p] @V2[p]
*PLOT TRAN -1 1 A=G A=IN A=OUT
*PLOT OP -1 1 A=G A=IN A=OUT
*Selected Circuit Analyses:
.TRAN 1E-5 0.002 0 1E-5
.OP
*Models and Subcircuit:
.MODEL 2N4393 NJF(VTO=-1.422 BETA=0.009109 LAMBDA=0.006 RD=1 RS=1 CGS=4.06E-12
+ CGD=4.57E-12 IS=2.052E-13 KF=1.23E-16 )
.END