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python-schdoc/tests/altium_crap/Soft Designs/Timing/DS1391 RTC/DS1391_RTC.Constraint

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initial commit of altium sample files and python code
2016-09-30 09:43:38 +00:00
;-------------------------------------------------------------------------------
;Constraints File
; Device : Any
; Board : Nanoboard 2
; Project : DS1391_RTC.PrjFpg
;
; Created 22-Nov-2008
; Altium Limited
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
Record=FileHeader | Id=DXP Constraints v1.0
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50 Mhz
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK_FREQUENCY=1 Mhz
;-------------------------------------------------------------------------------