;...............................................................................
;Constraints File
;   Device  :
;   Board   :
;   Project :
;
;   Created 3/04/2009
;...............................................................................

;...............................................................................
Record=FileHeader | Id=DXP Constraints v1.0
;...............................................................................


Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_PIN=True | FPGA_CLOCK_FREQUENCY=50 MHz