;-------------------------------------------------------------------------------
;Constraints File
;   Device  : Any
;   Board   : Nanoboard 2
;   Project : DSF_Slideshow.PrjFpg
;
;   Created 11-Dec-2006
;   Altium Limited
;-------------------------------------------------------------------------------

;-------------------------------------------------------------------------------
Record=FileHeader | Id=DXP Constraints v1.0
;-------------------------------------------------------------------------------

;-------------------------------------------------------------------------------
Record=Constraint | TargetKind=Port | TargetId=CLK_REF              | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_REF              | FPGA_CLOCK_FREQUENCY=20 Mhz
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD              | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD              | FPGA_CLOCK_FREQUENCY=50 Mhz
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK       | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK       | FPGA_CLOCK_FREQUENCY=5 Mhz
;-------------------------------------------------------------------------------


;-------------------------------------------------------------------------------
Record=Constraint | TargetKind=Port | TargetId=PHY_TXC              | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=PHY_TXC              | FPGA_CLOCK_FREQUENCY=25 Mhz
Record=Constraint | TargetKind=Port | TargetId=PHY_RXC              | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=PHY_RXC              | FPGA_CLOCK_FREQUENCY=25 Mhz
;-------------------------------------------------------------------------------