python-schdoc/altium_crap/Tutorials/Audio Effects Tutorial/MyConstraint.Constraint

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;...............................................................................
;Constraints File
; Device :
; Board :
; Project :
;
; Created 10/08/2008
;...............................................................................
;...............................................................................
Record=FileHeader | Id=DXP Constraints v1.0
;...............................................................................
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50MHz