python-schdoc/altium_crap/Tutorials/CHC Accumulator/CHC_Accumulator.Constraint

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;...............................................................................
;Constraints File
; Device : Any
; Board : Any
; Project : CHC_Accumulator.PrjFpg
;
; Created 5/05/2008
; Altiumm Limited
;...............................................................................
;...............................................................................
Record=FileHeader | Id=DXP Constraints v1.0
;...............................................................................
;...............................................................................
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50 Mhz
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK_FREQUENCY=1 Mhz
;...............................................................................