python-schdoc/altium_crap/Tutorials/NB3000 Discovery Series/Discovery Session 8/up_KR_Constraint.Constraint

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;...............................................................................
;Constraints File
; Device :
; Board :
; Project :
;
; Created 3/04/2009
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Record=FileHeader | Id=DXP Constraints v1.0
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Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_PIN=True | FPGA_CLOCK_FREQUENCY=50 MHz