69 lines
2.0 KiB
VHDL
69 lines
2.0 KiB
VHDL
--------------------------------------------------------------------------------
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-- SubModule shiftreg
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-- Created 2010/02/17 12:24:48
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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entity shiftreg is port
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(
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PARIN : in std_logic_vector(15 downto 0);
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START : in std_logic;
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READY : out std_logic;
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SEROUT : out std_logic;
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SCLK_I : in std_logic;
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RST_I : in std_logic;
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CLK_I : in std_logic
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);
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end shiftreg;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture Structure of shiftreg is
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-- Component Declarations
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-- Signal Declarations
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begin
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process( CLK_I )
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variable state : integer range 0 to PARIN'length + 1;
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variable shiftreg : std_logic_vector( PARIN'range );
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variable prevclk : std_logic;
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begin
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if rising_edge( CLK_I ) then
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if RST_I = '1' then
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READY <= '1';
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shiftreg := (others => '1');
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state := 0;
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SEROUT <= '1';
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elsif prevclk = '0' and SCLK_I = '1' then
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if state = 0 then
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SEROUT <= '1';
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if START = '1' then
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shiftreg := PARIN;
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READY <= '0';
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state := 1;
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else
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shiftreg( shiftreg'left ) := '1';
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end if;
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elsif state <= PARIN'length then
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SEROUT <= shiftreg( 0 );
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shiftreg := '1' & shiftreg( shiftreg'left downto 1 );
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state := state + 1;
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else
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SEROUT <= '1';
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READY <= '1';
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if START = '0' then
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state := 0;
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end if;
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end if;
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end if;
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prevclk := SCLK_I;
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end if;
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end process;
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end Structure;
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--------------------------------------------------------------------------------
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