28 lines
592 B
VHDL
28 lines
592 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity Clock_Divider is
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port (
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CLK_REF : in std_logic;
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CLK_OUT : out std_logic
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);
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end entity;
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architecture RTL of Clock_Divider is
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begin
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process(CLK_REF)
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variable i : integer range 0 to 999999;
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begin
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if rising_edge(CLK_REF) then
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if i = 0 then
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CLK_OUT <= '1';
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i := 999999;
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else
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CLK_OUT <= '0';
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i := i - 1;
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end if;
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end if;
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end process;
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end architecture;
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