35 lines
1.1 KiB
VHDL
35 lines
1.1 KiB
VHDL
-------------------------------------------------------------------
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ENTITY BrightnessPalette IS
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PORT( D : IN std_logic_vector(3 downto 0);
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Q : OUT std_logic_vector(7 downto 0)
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);
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end BrightnessPalette;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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Architecture RTL OF BrightnessPalette IS
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Begin
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Process(D)
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Begin
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Case D Is
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when X"0" => Q <= X"00";
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when X"1" => Q <= X"01";
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when X"2" => Q <= X"02";
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when X"3" => Q <= X"03";
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when X"4" => Q <= X"04";
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when X"5" => Q <= X"05";
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when X"6" => Q <= X"07";
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when X"7" => Q <= X"09";
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when X"8" => Q <= X"0E";
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when X"9" => Q <= X"16";
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when X"A" => Q <= X"21";
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when X"B" => Q <= X"32";
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when X"C" => Q <= X"4B";
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when X"D" => Q <= X"71";
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when X"E" => Q <= X"AA";
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when others => Q <= X"FF";
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End Case;
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End Process;
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End RTL;
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-------------------------------------------------------------------
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