python-schdoc/altium_crap/Soft Designs/Audio/CS4270 Audio Codec/CS4270_Audio_Codec.Constraint

21 lines
1.0 KiB
Plaintext

;-------------------------------------------------------------------------------
;Constraints File
; Device : Any
; Board : Nanoboard 2
; Project : CS4270_Audio_Codec.PrjFpg
;
; Created 20-Nov-2008
; Altium Limited
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
Record=FileHeader | Id=DXP Constraints v1.0
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50 Mhz
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK_FREQUENCY=1 Mhz
;-------------------------------------------------------------------------------