python-schdoc/altium_crap/Soft Designs/Audio/NB3000 Audio Service/NB3000_Audio_Service.Constr...

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;...............................................................................
;Constraints File
; Device : Any
; Board : NB3000
; Project : NB3000_Audio_Service.PrjFpg
;
; Created 10-3-2010
;...............................................................................
;...............................................................................
Record=FileHeader | Id=DXP Constraints v1.0
;...............................................................................
;-------------------------------------------------------------------------------
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50 Mhz
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=TRUE
Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK_FREQUENCY=1 Mhz
;-------------------------------------------------------------------------------