30 lines
1013 B
VHDL
30 lines
1013 B
VHDL
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-- SubModule TRange
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-- Created 15/11/2003 12:44:20 AM
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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entity TRange is port
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(
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lower : in std_logic_vector(15 downto 0);
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data : in std_logic_vector(15 downto 0);
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upper : in std_logic_vector(15 downto 0);
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-----
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isBetween : out std_logic;
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equalsLower : out std_logic;
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equalsUpper : out std_logic
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);
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end TRange;
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architecture structure of TRange is
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begin
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isBetween <= '1' when (data>=lower) and (data<=upper) else '0';
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equalsLower <= '1' when (data=lower) else '0';
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equalsUpper <= '1' when (data=upper) else '0';
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end structure;
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