18 lines
684 B
Plaintext
18 lines
684 B
Plaintext
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;Constraints File
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; Device :
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; Board :
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; Project :
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;
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; Created 30/03/2010
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Record=FileHeader | Id=DXP Constraints v1.0
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Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_PIN=True | FPGA_CLOCK_FREQUENCY=40 MHz
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Record=Constraint | TargetKind=Port | TargetId=JTAG_NEXUS_TCK | FPGA_CLOCK=True | FPGA_CLOCK_FREQUENCY=5 MHz
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