103 lines
2.6 KiB
Plaintext
103 lines
2.6 KiB
Plaintext
-- run to time 90 ns
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Library IEEE ;
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Use IEEE.std_logic_1164.all ;
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Use IEEE.std_logic_textio.all ;
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Library work;
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Use work.all;
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Library STD ;
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Use std.textio.all ;
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entity main_tb is
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end ;
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architecture test of main_tb is
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--*****************************************************************
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-- Write Results into file.
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--*****************************************************************
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file RESULTS: text open WRITE_MODE is "results.txt";
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procedure WRITE_RESULTS(
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CI : std_logic ;
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X : std_logic_vector ( 15 downto 0 ) ;
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Y : std_logic_vector ( 15 downto 0 ) ;
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CO : std_logic ;
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S : std_logic_vector ( 15 downto 0 )
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) is
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variable l_out : line ;
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begin
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write(l_out, now, right, 15, ps);
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-- write inputs
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write(l_out, CI, right, 2 ) ;
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write(l_out, X, right, 17 ) ;
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write(l_out, Y, right, 17 ) ;
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-- write outputs
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write(l_out, CO, right, 2 ) ;
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write(l_out, S, right, 17 ) ;
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writeline(results, l_out);
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end ;
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--*****************************************************************
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-- Design Under Test component declaration.
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--*****************************************************************
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component X_16Bit_Group_Ripple_Adder is
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port (
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CI : in std_logic ;
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CO : out std_logic ;
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S : out std_logic_vector( 15 downto 0 ) ;
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X : in std_logic_vector( 15 downto 0 ) ;
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Y : in std_logic_vector( 15 downto 0 )
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);
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end component ;
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signal CI, CO : std_logic ;
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signal S, X, Y : std_logic_vector( 15 downto 0 ) ;
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begin
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--*****************************************************************
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-- Design Under Test
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--*****************************************************************
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DUT : X_16Bit_Group_Ripple_Adder
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port map (
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CI => CI,
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X => X,
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Y => Y,
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CO => CO,
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S => S
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) ;
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STIMUL : process
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begin
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CI <= '0' ;
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X <= "1111111100000000" ;
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Y <= "1010101010101010" ;
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wait for 10 ns ;
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X <= "0010101101001101" ;
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wait for 10 ns ;
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CI <= '1' ;
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wait for 10 ns ;
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Y <= "1100000110111111" ;
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wait for 10 ns ;
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X <= "0001010111100010" ;
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wait for 10 ns ;
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CI <= '0' ;
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wait for 10 ns ;
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X <= "1101101100001000" ;
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wait for 10 ns ;
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X <= "1110101101000000" ;
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wait for 10 ns ;
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CI <= '1' ;
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wait for 10 ns ;
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Y <= "1100010101010001" ;
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wait for 10 ns ;
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wait ;
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end process ;
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WRITE_RESULTS( CI, X, Y, CO, S ) ;
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end test ;
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