3939 lines
372 KiB
Plaintext
3939 lines
372 KiB
Plaintext
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This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv
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COVERGROUP COVERAGE:
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----------------------------------------------------------------------------------------------------------
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Covergroup Metric Goal Status
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----------------------------------------------------------------------------------------------------------
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TYPE /riscv_instr_pkg/riscv_instr_cover_group/add_cg
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100.00% 100 Covered
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covered/total bins: 110 110
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missing/total bins: 0 110
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% Hit: 100.00% 100
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Coverpoint add_cg::cp_rs1 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 6 1 Covered
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bin auto[RA] 2 1 Covered
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bin auto[SP] 2 1 Covered
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bin auto[GP] 7 1 Covered
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bin auto[TP] 2 1 Covered
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bin auto[T0] 1 1 Covered
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bin auto[T1] 2 1 Covered
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bin auto[T2] 1 1 Covered
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bin auto[S0] 6 1 Covered
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bin auto[S1] 1 1 Covered
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bin auto[A0] 1 1 Covered
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bin auto[A1] 1 1 Covered
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bin auto[A2] 1 1 Covered
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bin auto[A3] 6 1 Covered
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bin auto[A4] 2 1 Covered
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bin auto[A5] 2 1 Covered
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bin auto[A6] 1 1 Covered
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bin auto[A7] 1 1 Covered
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bin auto[S2] 6 1 Covered
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bin auto[S3] 1 1 Covered
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bin auto[S4] 1 1 Covered
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bin auto[S5] 1 1 Covered
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bin auto[S6] 1 1 Covered
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bin auto[S7] 6 1 Covered
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bin auto[S8] 1 1 Covered
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bin auto[S9] 1 1 Covered
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bin auto[S10] 2 1 Covered
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bin auto[S11] 1 1 Covered
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bin auto[T3] 4 1 Covered
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bin auto[T4] 2 1 Covered
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bin auto[T5] 2 1 Covered
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bin auto[T6] 2 1 Covered
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Coverpoint add_cg::cp_rs2 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 8 1 Covered
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bin auto[RA] 2 1 Covered
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bin auto[SP] 1 1 Covered
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bin auto[GP] 1 1 Covered
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bin auto[TP] 2 1 Covered
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bin auto[T0] 3 1 Covered
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bin auto[T1] 2 1 Covered
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bin auto[T2] 2 1 Covered
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bin auto[S0] 2 1 Covered
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bin auto[S1] 2 1 Covered
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bin auto[A0] 2 1 Covered
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bin auto[A1] 2 1 Covered
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bin auto[A2] 2 1 Covered
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bin auto[A3] 2 1 Covered
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bin auto[A4] 2 1 Covered
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bin auto[A5] 2 1 Covered
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bin auto[A6] 3 1 Covered
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bin auto[A7] 2 1 Covered
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bin auto[S2] 2 1 Covered
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bin auto[S3] 2 1 Covered
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bin auto[S4] 2 1 Covered
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bin auto[S5] 2 1 Covered
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bin auto[S6] 2 1 Covered
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bin auto[S7] 2 1 Covered
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bin auto[S8] 2 1 Covered
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bin auto[S9] 3 1 Covered
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bin auto[S10] 2 1 Covered
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bin auto[S11] 10 1 Covered
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bin auto[T3] 2 1 Covered
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bin auto[T4] 1 1 Covered
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bin auto[T5] 1 1 Covered
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bin auto[T6] 1 1 Covered
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Coverpoint add_cg::cp_rd 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 4 1 Covered
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bin auto[RA] 2 1 Covered
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bin auto[SP] 2 1 Covered
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bin auto[GP] 2 1 Covered
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bin auto[TP] 3 1 Covered
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bin auto[T0] 4 1 Covered
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bin auto[T1] 3 1 Covered
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bin auto[T2] 2 1 Covered
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bin auto[S0] 2 1 Covered
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bin auto[S1] 2 1 Covered
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bin auto[A0] 2 1 Covered
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bin auto[A1] 2 1 Covered
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bin auto[A2] 2 1 Covered
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bin auto[A3] 2 1 Covered
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bin auto[A4] 3 1 Covered
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bin auto[A5] 3 1 Covered
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bin auto[A6] 3 1 Covered
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bin auto[A7] 2 1 Covered
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bin auto[S2] 2 1 Covered
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bin auto[S3] 2 1 Covered
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bin auto[S4] 2 1 Covered
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bin auto[S5] 2 1 Covered
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bin auto[S6] 2 1 Covered
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bin auto[S7] 2 1 Covered
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bin auto[S8] 2 1 Covered
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bin auto[S9] 3 1 Covered
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bin auto[S10] 3 1 Covered
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bin auto[S11] 3 1 Covered
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bin auto[T3] 2 1 Covered
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bin auto[T4] 2 1 Covered
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bin auto[T5] 2 1 Covered
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bin auto[T6] 2 1 Covered
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Coverpoint add_cg::cp_rs1_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 53 1 Covered
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bin auto[NEGATIVE] 23 1 Covered
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Coverpoint add_cg::cp_rs2_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 52 1 Covered
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bin auto[NEGATIVE] 24 1 Covered
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Coverpoint add_cg::cp_rd_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 43 1 Covered
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bin auto[NEGATIVE] 33 1 Covered
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Cross add_cg::cp_sign_cross 100.00% 100 Covered
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covered/total bins: 8 8
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missing/total bins: 0 8
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% Hit: 100.00% 100
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bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]>
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29 1 Covered
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bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]>
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5 1 Covered
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bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]>
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5 1 Covered
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bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]>
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4 1 Covered
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bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]>
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7 1 Covered
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bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]>
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11 1 Covered
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bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]>
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12 1 Covered
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bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]>
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3 1 Covered
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TYPE /riscv_instr_pkg/riscv_instr_cover_group/sub_cg
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98.21% 100 Uncovered
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covered/total bins: 109 110
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missing/total bins: 1 110
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% Hit: 99.09% 100
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Coverpoint sub_cg::cp_rs1 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 3 1 Covered
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bin auto[RA] 2 1 Covered
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bin auto[SP] 2 1 Covered
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bin auto[GP] 2 1 Covered
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bin auto[TP] 2 1 Covered
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bin auto[T0] 2 1 Covered
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bin auto[T1] 2 1 Covered
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bin auto[T2] 2 1 Covered
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bin auto[S0] 2 1 Covered
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bin auto[S1] 3 1 Covered
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bin auto[A0] 2 1 Covered
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bin auto[A1] 2 1 Covered
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bin auto[A2] 2 1 Covered
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bin auto[A3] 2 1 Covered
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bin auto[A4] 2 1 Covered
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bin auto[A5] 2 1 Covered
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bin auto[A6] 2 1 Covered
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bin auto[A7] 2 1 Covered
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bin auto[S2] 2 1 Covered
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bin auto[S3] 2 1 Covered
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bin auto[S4] 2 1 Covered
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bin auto[S5] 2 1 Covered
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bin auto[S6] 2 1 Covered
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bin auto[S7] 2 1 Covered
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bin auto[S8] 2 1 Covered
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bin auto[S9] 2 1 Covered
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bin auto[S10] 2 1 Covered
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bin auto[S11] 2 1 Covered
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bin auto[T3] 2 1 Covered
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bin auto[T4] 2 1 Covered
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bin auto[T5] 2 1 Covered
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bin auto[T6] 2 1 Covered
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Coverpoint sub_cg::cp_rs2 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 1 1 Covered
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bin auto[RA] 21 1 Covered
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bin auto[SP] 8 1 Covered
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bin auto[GP] 1 1 Covered
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bin auto[TP] 1 1 Covered
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bin auto[T0] 6 1 Covered
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bin auto[T1] 1 1 Covered
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bin auto[T2] 1 1 Covered
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bin auto[S0] 3 1 Covered
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bin auto[S1] 1 1 Covered
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bin auto[A0] 1 1 Covered
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bin auto[A1] 1 1 Covered
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bin auto[A2] 1 1 Covered
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bin auto[A3] 1 1 Covered
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bin auto[A4] 1 1 Covered
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bin auto[A5] 1 1 Covered
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bin auto[A6] 1 1 Covered
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bin auto[A7] 1 1 Covered
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bin auto[S2] 1 1 Covered
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bin auto[S3] 1 1 Covered
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bin auto[S4] 1 1 Covered
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bin auto[S5] 1 1 Covered
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bin auto[S6] 1 1 Covered
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bin auto[S7] 1 1 Covered
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bin auto[S8] 1 1 Covered
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bin auto[S9] 1 1 Covered
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bin auto[S10] 1 1 Covered
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bin auto[S11] 1 1 Covered
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bin auto[T3] 1 1 Covered
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bin auto[T4] 1 1 Covered
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bin auto[T5] 1 1 Covered
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bin auto[T6] 1 1 Covered
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Coverpoint sub_cg::cp_rd 100.00% 100 Covered
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covered/total bins: 32 32
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missing/total bins: 0 32
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% Hit: 100.00% 100
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bin auto[ZERO] 3 1 Covered
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bin auto[RA] 2 1 Covered
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bin auto[SP] 2 1 Covered
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bin auto[GP] 2 1 Covered
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bin auto[TP] 2 1 Covered
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bin auto[T0] 2 1 Covered
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bin auto[T1] 2 1 Covered
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bin auto[T2] 2 1 Covered
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bin auto[S0] 2 1 Covered
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bin auto[S1] 3 1 Covered
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bin auto[A0] 2 1 Covered
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bin auto[A1] 2 1 Covered
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bin auto[A2] 2 1 Covered
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bin auto[A3] 2 1 Covered
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bin auto[A4] 2 1 Covered
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bin auto[A5] 2 1 Covered
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bin auto[A6] 2 1 Covered
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bin auto[A7] 2 1 Covered
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bin auto[S2] 2 1 Covered
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bin auto[S3] 2 1 Covered
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bin auto[S4] 2 1 Covered
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bin auto[S5] 2 1 Covered
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bin auto[S6] 2 1 Covered
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bin auto[S7] 2 1 Covered
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bin auto[S8] 2 1 Covered
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bin auto[S9] 2 1 Covered
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bin auto[S10] 2 1 Covered
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bin auto[S11] 2 1 Covered
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bin auto[T3] 2 1 Covered
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bin auto[T4] 2 1 Covered
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bin auto[T5] 2 1 Covered
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bin auto[T6] 2 1 Covered
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Coverpoint sub_cg::cp_rs1_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 26 1 Covered
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bin auto[NEGATIVE] 40 1 Covered
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Coverpoint sub_cg::cp_rs2_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 21 1 Covered
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bin auto[NEGATIVE] 45 1 Covered
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Coverpoint sub_cg::cp_rd_sign 100.00% 100 Covered
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covered/total bins: 2 2
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missing/total bins: 0 2
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% Hit: 100.00% 100
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bin auto[POSITIVE] 47 1 Covered
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bin auto[NEGATIVE] 19 1 Covered
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Cross sub_cg::cp_sign_cross 87.50% 100 Uncovered
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covered/total bins: 7 8
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missing/total bins: 1 8
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% Hit: 87.50% 100
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bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]>
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7 1 Covered
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bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]>
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1 1 Covered
|
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bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]>
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9 1 Covered
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bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]>
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|
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30 1 Covered
|
||
|
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bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]>
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|
|
4 1 Covered
|
||
|
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bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]>
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|
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9 1 Covered
|
||
|
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bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]>
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|
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6 1 Covered
|
||
|
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bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]>
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||
|
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0 1 ZERO
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||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/addi_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 78 78
|
||
|
|
missing/total bins: 0 78
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint addi_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1237 1 Covered
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bin auto[RA] 556 1 Covered
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bin auto[SP] 178 1 Covered
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bin auto[GP] 50 1 Covered
|
||
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bin auto[TP] 23 1 Covered
|
||
|
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bin auto[T0] 376 1 Covered
|
||
|
|
bin auto[T1] 26 1 Covered
|
||
|
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bin auto[T2] 36 1 Covered
|
||
|
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bin auto[S0] 48 1 Covered
|
||
|
|
bin auto[S1] 38 1 Covered
|
||
|
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bin auto[A0] 86 1 Covered
|
||
|
|
bin auto[A1] 26 1 Covered
|
||
|
|
bin auto[A2] 11 1 Covered
|
||
|
|
bin auto[A3] 23 1 Covered
|
||
|
|
bin auto[A4] 10 1 Covered
|
||
|
|
bin auto[A5] 10 1 Covered
|
||
|
|
bin auto[A6] 13 1 Covered
|
||
|
|
bin auto[A7] 12 1 Covered
|
||
|
|
bin auto[S2] 10 1 Covered
|
||
|
|
bin auto[S3] 35 1 Covered
|
||
|
|
bin auto[S4] 13 1 Covered
|
||
|
|
bin auto[S5] 35 1 Covered
|
||
|
|
bin auto[S6] 27 1 Covered
|
||
|
|
bin auto[S7] 23 1 Covered
|
||
|
|
bin auto[S8] 48 1 Covered
|
||
|
|
bin auto[S9] 39 1 Covered
|
||
|
|
bin auto[S10] 39 1 Covered
|
||
|
|
bin auto[S11] 29 1 Covered
|
||
|
|
bin auto[T3] 10 1 Covered
|
||
|
|
bin auto[T4] 23 1 Covered
|
||
|
|
bin auto[T5] 34 1 Covered
|
||
|
|
bin auto[T6] 15 1 Covered
|
||
|
|
Coverpoint addi_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 9 1 Covered
|
||
|
|
bin auto[RA] 549 1 Covered
|
||
|
|
bin auto[SP] 208 1 Covered
|
||
|
|
bin auto[GP] 170 1 Covered
|
||
|
|
bin auto[TP] 46 1 Covered
|
||
|
|
bin auto[T0] 494 1 Covered
|
||
|
|
bin auto[T1] 77 1 Covered
|
||
|
|
bin auto[T2] 73 1 Covered
|
||
|
|
bin auto[S0] 60 1 Covered
|
||
|
|
bin auto[S1] 60 1 Covered
|
||
|
|
bin auto[A0] 156 1 Covered
|
||
|
|
bin auto[A1] 60 1 Covered
|
||
|
|
bin auto[A2] 47 1 Covered
|
||
|
|
bin auto[A3] 59 1 Covered
|
||
|
|
bin auto[A4] 60 1 Covered
|
||
|
|
bin auto[A5] 60 1 Covered
|
||
|
|
bin auto[A6] 63 1 Covered
|
||
|
|
bin auto[A7] 61 1 Covered
|
||
|
|
bin auto[S2] 59 1 Covered
|
||
|
|
bin auto[S3] 60 1 Covered
|
||
|
|
bin auto[S4] 35 1 Covered
|
||
|
|
bin auto[S5] 57 1 Covered
|
||
|
|
bin auto[S6] 60 1 Covered
|
||
|
|
bin auto[S7] 59 1 Covered
|
||
|
|
bin auto[S8] 60 1 Covered
|
||
|
|
bin auto[S9] 61 1 Covered
|
||
|
|
bin auto[S10] 61 1 Covered
|
||
|
|
bin auto[S11] 63 1 Covered
|
||
|
|
bin auto[T3] 46 1 Covered
|
||
|
|
bin auto[T4] 59 1 Covered
|
||
|
|
bin auto[T5] 83 1 Covered
|
||
|
|
bin auto[T6] 64 1 Covered
|
||
|
|
Coverpoint addi_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 1995 1 Covered
|
||
|
|
bin auto[NEGATIVE] 1144 1 Covered
|
||
|
|
Coverpoint addi_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 1692 1 Covered
|
||
|
|
bin auto[NEGATIVE] 1447 1 Covered
|
||
|
|
Coverpoint addi_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 1531 1 Covered
|
||
|
|
bin auto[NEGATIVE] 1608 1 Covered
|
||
|
|
Cross addi_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 8 8
|
||
|
|
missing/total bins: 0 8
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]>
|
||
|
|
1148 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]>
|
||
|
|
1 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]>
|
||
|
|
456 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]>
|
||
|
|
87 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]>
|
||
|
|
2 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]>
|
||
|
|
380 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]>
|
||
|
|
389 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]>
|
||
|
|
676 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lui_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 34 34
|
||
|
|
missing/total bins: 0 34
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint lui_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 5 1 Covered
|
||
|
|
bin auto[RA] 274 1 Covered
|
||
|
|
bin auto[SP] 46 1 Covered
|
||
|
|
bin auto[GP] 29 1 Covered
|
||
|
|
bin auto[TP] 32 1 Covered
|
||
|
|
bin auto[T0] 34 1 Covered
|
||
|
|
bin auto[T1] 20 1 Covered
|
||
|
|
bin auto[T2] 18 1 Covered
|
||
|
|
bin auto[S0] 43 1 Covered
|
||
|
|
bin auto[S1] 32 1 Covered
|
||
|
|
bin auto[A0] 80 1 Covered
|
||
|
|
bin auto[A1] 20 1 Covered
|
||
|
|
bin auto[A2] 18 1 Covered
|
||
|
|
bin auto[A3] 18 1 Covered
|
||
|
|
bin auto[A4] 4 1 Covered
|
||
|
|
bin auto[A5] 4 1 Covered
|
||
|
|
bin auto[A6] 4 1 Covered
|
||
|
|
bin auto[A7] 5 1 Covered
|
||
|
|
bin auto[S2] 5 1 Covered
|
||
|
|
bin auto[S3] 29 1 Covered
|
||
|
|
bin auto[S4] 32 1 Covered
|
||
|
|
bin auto[S5] 32 1 Covered
|
||
|
|
bin auto[S6] 21 1 Covered
|
||
|
|
bin auto[S7] 18 1 Covered
|
||
|
|
bin auto[S8] 42 1 Covered
|
||
|
|
bin auto[S9] 32 1 Covered
|
||
|
|
bin auto[S10] 32 1 Covered
|
||
|
|
bin auto[S11] 23 1 Covered
|
||
|
|
bin auto[T3] 18 1 Covered
|
||
|
|
bin auto[T4] 17 1 Covered
|
||
|
|
bin auto[T5] 4 1 Covered
|
||
|
|
bin auto[T6] 4 1 Covered
|
||
|
|
Coverpoint lui_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 723 1 Covered
|
||
|
|
bin auto[NEGATIVE] 272 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/auipc_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 34 34
|
||
|
|
missing/total bins: 0 34
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint auipc_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 196 1 Covered
|
||
|
|
bin auto[SP] 106 1 Covered
|
||
|
|
bin auto[GP] 22 1 Covered
|
||
|
|
bin auto[TP] 17 1 Covered
|
||
|
|
bin auto[T0] 331 1 Covered
|
||
|
|
bin auto[T1] 7 1 Covered
|
||
|
|
bin auto[T2] 19 1 Covered
|
||
|
|
bin auto[S0] 8 1 Covered
|
||
|
|
bin auto[S1] 8 1 Covered
|
||
|
|
bin auto[A0] 7 1 Covered
|
||
|
|
bin auto[A1] 7 1 Covered
|
||
|
|
bin auto[A2] 7 1 Covered
|
||
|
|
bin auto[A3] 7 1 Covered
|
||
|
|
bin auto[A4] 7 1 Covered
|
||
|
|
bin auto[A5] 7 1 Covered
|
||
|
|
bin auto[A6] 10 1 Covered
|
||
|
|
bin auto[A7] 8 1 Covered
|
||
|
|
bin auto[S2] 7 1 Covered
|
||
|
|
bin auto[S3] 7 1 Covered
|
||
|
|
bin auto[S4] 7 1 Covered
|
||
|
|
bin auto[S5] 7 1 Covered
|
||
|
|
bin auto[S6] 7 1 Covered
|
||
|
|
bin auto[S7] 7 1 Covered
|
||
|
|
bin auto[S8] 7 1 Covered
|
||
|
|
bin auto[S9] 8 1 Covered
|
||
|
|
bin auto[S10] 8 1 Covered
|
||
|
|
bin auto[S11] 7 1 Covered
|
||
|
|
bin auto[T3] 7 1 Covered
|
||
|
|
bin auto[T4] 7 1 Covered
|
||
|
|
bin auto[T5] 7 1 Covered
|
||
|
|
bin auto[T6] 12 1 Covered
|
||
|
|
Coverpoint auipc_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 54 1 Covered
|
||
|
|
bin auto[NEGATIVE] 827 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sra_cg
|
||
|
|
85.71% 100 Uncovered
|
||
|
|
covered/total bins: 103 106
|
||
|
|
missing/total bins: 3 106
|
||
|
|
% Hit: 97.16% 100
|
||
|
|
Coverpoint sra_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sra_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sra_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sra_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint sra_cg::cp_rs2_sign 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[POSITIVE] 33 1 Covered
|
||
|
|
bin auto[NEGATIVE] 0 1 ZERO
|
||
|
|
Coverpoint sra_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 22 1 Covered
|
||
|
|
bin auto[NEGATIVE] 11 1 Covered
|
||
|
|
Cross sra_cg::cp_sign_cross 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 2 4
|
||
|
|
missing/total bins: 2 4
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sll_cg
|
||
|
|
85.71% 100 Uncovered
|
||
|
|
covered/total bins: 103 106
|
||
|
|
missing/total bins: 3 106
|
||
|
|
% Hit: 97.16% 100
|
||
|
|
Coverpoint sll_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sll_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sll_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sll_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint sll_cg::cp_rs2_sign 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[POSITIVE] 33 1 Covered
|
||
|
|
bin auto[NEGATIVE] 0 1 ZERO
|
||
|
|
Coverpoint sll_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 22 1 Covered
|
||
|
|
bin auto[NEGATIVE] 11 1 Covered
|
||
|
|
Cross sll_cg::cp_sign_cross 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 2 4
|
||
|
|
missing/total bins: 2 4
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/srl_cg
|
||
|
|
85.71% 100 Uncovered
|
||
|
|
covered/total bins: 103 106
|
||
|
|
missing/total bins: 3 106
|
||
|
|
% Hit: 97.16% 100
|
||
|
|
Coverpoint srl_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srl_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 2 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srl_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srl_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint srl_cg::cp_rs2_sign 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[POSITIVE] 33 1 Covered
|
||
|
|
bin auto[NEGATIVE] 0 1 ZERO
|
||
|
|
Coverpoint srl_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 30 1 Covered
|
||
|
|
bin auto[NEGATIVE] 3 1 Covered
|
||
|
|
Cross srl_cg::cp_sign_cross 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 2 4
|
||
|
|
missing/total bins: 2 4
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/srai_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 68 68
|
||
|
|
missing/total bins: 0 68
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint srai_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srai_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srai_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint srai_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 22 1 Covered
|
||
|
|
bin auto[NEGATIVE] 11 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/slli_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 68 68
|
||
|
|
missing/total bins: 0 68
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint slli_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 2 1 Covered
|
||
|
|
bin auto[TP] 2 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 2 1 Covered
|
||
|
|
bin auto[S0] 2 1 Covered
|
||
|
|
bin auto[S1] 2 1 Covered
|
||
|
|
bin auto[A0] 50 1 Covered
|
||
|
|
bin auto[A1] 2 1 Covered
|
||
|
|
bin auto[A2] 2 1 Covered
|
||
|
|
bin auto[A3] 2 1 Covered
|
||
|
|
bin auto[A4] 2 1 Covered
|
||
|
|
bin auto[A5] 2 1 Covered
|
||
|
|
bin auto[A6] 2 1 Covered
|
||
|
|
bin auto[A7] 2 1 Covered
|
||
|
|
bin auto[S2] 2 1 Covered
|
||
|
|
bin auto[S3] 2 1 Covered
|
||
|
|
bin auto[S4] 2 1 Covered
|
||
|
|
bin auto[S5] 2 1 Covered
|
||
|
|
bin auto[S6] 2 1 Covered
|
||
|
|
bin auto[S7] 2 1 Covered
|
||
|
|
bin auto[S8] 2 1 Covered
|
||
|
|
bin auto[S9] 2 1 Covered
|
||
|
|
bin auto[S10] 2 1 Covered
|
||
|
|
bin auto[S11] 2 1 Covered
|
||
|
|
bin auto[T3] 2 1 Covered
|
||
|
|
bin auto[T4] 2 1 Covered
|
||
|
|
bin auto[T5] 2 1 Covered
|
||
|
|
bin auto[T6] 2 1 Covered
|
||
|
|
Coverpoint slli_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 2 1 Covered
|
||
|
|
bin auto[TP] 2 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 2 1 Covered
|
||
|
|
bin auto[S0] 2 1 Covered
|
||
|
|
bin auto[S1] 2 1 Covered
|
||
|
|
bin auto[A0] 50 1 Covered
|
||
|
|
bin auto[A1] 2 1 Covered
|
||
|
|
bin auto[A2] 2 1 Covered
|
||
|
|
bin auto[A3] 2 1 Covered
|
||
|
|
bin auto[A4] 2 1 Covered
|
||
|
|
bin auto[A5] 2 1 Covered
|
||
|
|
bin auto[A6] 2 1 Covered
|
||
|
|
bin auto[A7] 2 1 Covered
|
||
|
|
bin auto[S2] 2 1 Covered
|
||
|
|
bin auto[S3] 2 1 Covered
|
||
|
|
bin auto[S4] 2 1 Covered
|
||
|
|
bin auto[S5] 2 1 Covered
|
||
|
|
bin auto[S6] 2 1 Covered
|
||
|
|
bin auto[S7] 2 1 Covered
|
||
|
|
bin auto[S8] 2 1 Covered
|
||
|
|
bin auto[S9] 2 1 Covered
|
||
|
|
bin auto[S10] 2 1 Covered
|
||
|
|
bin auto[S11] 2 1 Covered
|
||
|
|
bin auto[T3] 2 1 Covered
|
||
|
|
bin auto[T4] 2 1 Covered
|
||
|
|
bin auto[T5] 2 1 Covered
|
||
|
|
bin auto[T6] 2 1 Covered
|
||
|
|
Coverpoint slli_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 100 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint slli_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 22 1 Covered
|
||
|
|
bin auto[NEGATIVE] 90 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/srli_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 68 68
|
||
|
|
missing/total bins: 0 68
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint srli_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srli_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint srli_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint srli_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 30 1 Covered
|
||
|
|
bin auto[NEGATIVE] 3 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/xor_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 110 110
|
||
|
|
missing/total bins: 0 110
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint xor_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 2 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 20 1 Covered
|
||
|
|
bin auto[NEGATIVE] 13 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 14 1 Covered
|
||
|
|
bin auto[NEGATIVE] 19 1 Covered
|
||
|
|
Coverpoint xor_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 4 1 Covered
|
||
|
|
bin auto[DIFFERENT] 21 1 Covered
|
||
|
|
Cross xor_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 11 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/or_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 110 110
|
||
|
|
missing/total bins: 0 110
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint or_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint or_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint or_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint or_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint or_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint or_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 12 1 Covered
|
||
|
|
bin auto[NEGATIVE] 21 1 Covered
|
||
|
|
Coverpoint or_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 4 1 Covered
|
||
|
|
bin auto[DIFFERENT] 21 1 Covered
|
||
|
|
Cross or_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/and_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 110 110
|
||
|
|
missing/total bins: 0 110
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint and_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint and_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 2 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint and_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint and_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint and_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint and_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 31 1 Covered
|
||
|
|
bin auto[NEGATIVE] 2 1 Covered
|
||
|
|
Coverpoint and_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 4 1 Covered
|
||
|
|
bin auto[DIFFERENT] 21 1 Covered
|
||
|
|
Cross and_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/xori_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 78 78
|
||
|
|
missing/total bins: 0 78
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint xori_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint xori_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint xori_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint xori_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 10 1 Covered
|
||
|
|
bin auto[NEGATIVE] 23 1 Covered
|
||
|
|
Coverpoint xori_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 12 1 Covered
|
||
|
|
bin auto[NEGATIVE] 21 1 Covered
|
||
|
|
Coverpoint xori_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 2 1 Covered
|
||
|
|
bin auto[DIFFERENT] 23 1 Covered
|
||
|
|
Cross xori_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 4 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 17 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/ori_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 78 78
|
||
|
|
missing/total bins: 0 78
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint ori_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint ori_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint ori_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint ori_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 6 1 Covered
|
||
|
|
bin auto[NEGATIVE] 27 1 Covered
|
||
|
|
Coverpoint ori_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 13 1 Covered
|
||
|
|
bin auto[NEGATIVE] 20 1 Covered
|
||
|
|
Coverpoint ori_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 3 1 Covered
|
||
|
|
bin auto[DIFFERENT] 22 1 Covered
|
||
|
|
Cross ori_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/andi_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 78 78
|
||
|
|
missing/total bins: 0 78
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint andi_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 24 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint andi_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 24 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint andi_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 35 1 Covered
|
||
|
|
Coverpoint andi_cg::cp_rd_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 52 1 Covered
|
||
|
|
bin auto[NEGATIVE] 4 1 Covered
|
||
|
|
Coverpoint andi_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 36 1 Covered
|
||
|
|
bin auto[NEGATIVE] 20 1 Covered
|
||
|
|
Coverpoint andi_cg::cp_logical 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[IDENTICAL] 4 1 Covered
|
||
|
|
bin auto[OPPOSITE] 4 1 Covered
|
||
|
|
bin auto[SIMILAR] 12 1 Covered
|
||
|
|
bin auto[DIFFERENT] 36 1 Covered
|
||
|
|
Cross andi_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 31 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/slt_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 106 106
|
||
|
|
missing/total bins: 0 106
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint slt_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint slt_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint slt_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint slt_cg::cp_result 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 20 1 Covered
|
||
|
|
bin auto[1] 13 1 Covered
|
||
|
|
Coverpoint slt_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint slt_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Cross slt_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltu_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 106 106
|
||
|
|
missing/total bins: 0 106
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint sltu_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sltu_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sltu_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint sltu_cg::cp_result 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 19 1 Covered
|
||
|
|
bin auto[1] 14 1 Covered
|
||
|
|
Coverpoint sltu_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sltu_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Cross sltu_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/slti_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 74 74
|
||
|
|
missing/total bins: 0 74
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint slti_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint slti_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint slti_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint slti_cg::cp_result 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 26 1 Covered
|
||
|
|
bin auto[1] 7 1 Covered
|
||
|
|
Coverpoint slti_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 13 1 Covered
|
||
|
|
bin auto[NEGATIVE] 20 1 Covered
|
||
|
|
Cross slti_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltiu_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 74 74
|
||
|
|
missing/total bins: 0 74
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint sltiu_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sltiu_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sltiu_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint sltiu_cg::cp_result 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 17 1 Covered
|
||
|
|
bin auto[1] 16 1 Covered
|
||
|
|
Coverpoint sltiu_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 13 1 Covered
|
||
|
|
bin auto[NEGATIVE] 20 1 Covered
|
||
|
|
Cross sltiu_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/beq_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint beq_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 52 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint beq_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 49 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 3 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint beq_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 71 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint beq_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 71 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint beq_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 77 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint beq_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 29 1 Covered
|
||
|
|
bin auto[1] 54 1 Covered
|
||
|
|
Cross beq_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 61 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/bne_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint bne_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 4 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 49 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bne_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 49 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bne_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 71 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bne_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 71 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bne_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 77 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint bne_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 30 1 Covered
|
||
|
|
bin auto[1] 53 1 Covered
|
||
|
|
Cross bne_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 61 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/blt_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint blt_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 2 1 Covered
|
||
|
|
bin auto[TP] 2 1 Covered
|
||
|
|
bin auto[T0] 4 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 2 1 Covered
|
||
|
|
bin auto[S0] 2 1 Covered
|
||
|
|
bin auto[S1] 2 1 Covered
|
||
|
|
bin auto[A0] 50 1 Covered
|
||
|
|
bin auto[A1] 2 1 Covered
|
||
|
|
bin auto[A2] 2 1 Covered
|
||
|
|
bin auto[A3] 2 1 Covered
|
||
|
|
bin auto[A4] 2 1 Covered
|
||
|
|
bin auto[A5] 2 1 Covered
|
||
|
|
bin auto[A6] 2 1 Covered
|
||
|
|
bin auto[A7] 2 1 Covered
|
||
|
|
bin auto[S2] 2 1 Covered
|
||
|
|
bin auto[S3] 2 1 Covered
|
||
|
|
bin auto[S4] 2 1 Covered
|
||
|
|
bin auto[S5] 2 1 Covered
|
||
|
|
bin auto[S6] 2 1 Covered
|
||
|
|
bin auto[S7] 2 1 Covered
|
||
|
|
bin auto[S8] 2 1 Covered
|
||
|
|
bin auto[S9] 2 1 Covered
|
||
|
|
bin auto[S10] 2 1 Covered
|
||
|
|
bin auto[S11] 2 1 Covered
|
||
|
|
bin auto[T3] 2 1 Covered
|
||
|
|
bin auto[T4] 2 1 Covered
|
||
|
|
bin auto[T5] 2 1 Covered
|
||
|
|
bin auto[T6] 2 1 Covered
|
||
|
|
Coverpoint blt_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 80 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint blt_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 91 1 Covered
|
||
|
|
Coverpoint blt_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 102 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint blt_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 108 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint blt_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 19 1 Covered
|
||
|
|
bin auto[1] 95 1 Covered
|
||
|
|
Cross blt_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 89 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/bge_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint bge_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bge_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 3 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bge_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bge_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bge_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 29 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint bge_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 19 1 Covered
|
||
|
|
bin auto[1] 16 1 Covered
|
||
|
|
Cross bge_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/bltu_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint bltu_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 3 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bltu_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bltu_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bltu_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bltu_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 29 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint bltu_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 19 1 Covered
|
||
|
|
bin auto[1] 16 1 Covered
|
||
|
|
Cross bltu_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/bgeu_cg
|
||
|
|
100.00% 100 Covered
|
||
|
|
covered/total bins: 76 76
|
||
|
|
missing/total bins: 0 76
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
Coverpoint bgeu_cg::cp_rs1 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 3 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bgeu_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 3 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint bgeu_cg::cp_rs1_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bgeu_cg::cp_rs2_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 23 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
Coverpoint bgeu_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 29 1 Covered
|
||
|
|
bin auto[NEGATIVE] 6 1 Covered
|
||
|
|
Coverpoint bgeu_cg::cp_branch_hit 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 19 1 Covered
|
||
|
|
bin auto[1] 16 1 Covered
|
||
|
|
Cross bgeu_cg::cp_sign_cross 100.00% 100 Covered
|
||
|
|
covered/total bins: 4 4
|
||
|
|
missing/total bins: 0 4
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered
|
||
|
|
bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered
|
||
|
|
bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lb_cg
|
||
|
|
98.95% 100 Uncovered
|
||
|
|
covered/total bins: 65 66
|
||
|
|
missing/total bins: 1 66
|
||
|
|
% Hit: 98.48% 100
|
||
|
|
Coverpoint lb_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 3 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lb_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lb_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 21 1 Covered
|
||
|
|
bin auto[NEGATIVE] 12 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lh_cg
|
||
|
|
99.21% 100 Uncovered
|
||
|
|
covered/total bins: 67 68
|
||
|
|
missing/total bins: 1 68
|
||
|
|
% Hit: 98.52% 100
|
||
|
|
Coverpoint lh_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 3 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 5 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lh_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 5 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lh_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 29 1 Covered
|
||
|
|
bin auto[NEGATIVE] 8 1 Covered
|
||
|
|
Coverpoint lh_cg::cp_align 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 35 1 Covered
|
||
|
|
bin auto[1] 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lw_cg
|
||
|
|
99.21% 100 Uncovered
|
||
|
|
covered/total bins: 67 68
|
||
|
|
missing/total bins: 1 68
|
||
|
|
% Hit: 98.52% 100
|
||
|
|
Coverpoint lw_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 11 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 5 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 2 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 2 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lw_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 3 1 Covered
|
||
|
|
bin auto[TP] 5 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 2 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 2 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 2 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 2 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 4 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lw_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 43 1 Covered
|
||
|
|
bin auto[NEGATIVE] 4 1 Covered
|
||
|
|
Coverpoint lw_cg::cp_align 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 44 1 Covered
|
||
|
|
bin auto[1] 3 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lbu_cg
|
||
|
|
98.95% 100 Uncovered
|
||
|
|
covered/total bins: 65 66
|
||
|
|
missing/total bins: 1 66
|
||
|
|
% Hit: 98.48% 100
|
||
|
|
Coverpoint lbu_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 3 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 6 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lbu_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 2 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 2 1 Covered
|
||
|
|
bin auto[T0] 2 1 Covered
|
||
|
|
bin auto[T1] 2 1 Covered
|
||
|
|
bin auto[T2] 2 1 Covered
|
||
|
|
bin auto[S0] 2 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lbu_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 25 1 Covered
|
||
|
|
bin auto[NEGATIVE] 13 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/lhu_cg
|
||
|
|
99.21% 100 Uncovered
|
||
|
|
covered/total bins: 67 68
|
||
|
|
missing/total bins: 1 68
|
||
|
|
% Hit: 98.52% 100
|
||
|
|
Coverpoint lhu_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 2 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 5 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 3 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lhu_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 1 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 2 1 Covered
|
||
|
|
bin auto[GP] 2 1 Covered
|
||
|
|
bin auto[TP] 5 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint lhu_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 30 1 Covered
|
||
|
|
bin auto[NEGATIVE] 8 1 Covered
|
||
|
|
Coverpoint lhu_cg::cp_align 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 36 1 Covered
|
||
|
|
bin auto[1] 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sb_cg
|
||
|
|
98.95% 100 Uncovered
|
||
|
|
covered/total bins: 65 66
|
||
|
|
missing/total bins: 1 66
|
||
|
|
% Hit: 98.48% 100
|
||
|
|
Coverpoint sb_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 22 1 Covered
|
||
|
|
bin auto[SP] 8 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 6 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sb_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 33 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sb_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 40 1 Covered
|
||
|
|
bin auto[NEGATIVE] 24 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sh_cg
|
||
|
|
99.21% 100 Uncovered
|
||
|
|
covered/total bins: 67 68
|
||
|
|
missing/total bins: 1 68
|
||
|
|
% Hit: 98.52% 100
|
||
|
|
Coverpoint sh_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 22 1 Covered
|
||
|
|
bin auto[SP] 12 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 6 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sh_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 33 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 5 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint sh_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 52 1 Covered
|
||
|
|
bin auto[NEGATIVE] 16 1 Covered
|
||
|
|
Coverpoint sh_cg::cp_misalign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 66 1 Covered
|
||
|
|
bin auto[1] 2 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/sw_cg
|
||
|
|
99.21% 100 Uncovered
|
||
|
|
covered/total bins: 67 68
|
||
|
|
missing/total bins: 1 68
|
||
|
|
% Hit: 98.52% 100
|
||
|
|
Coverpoint sw_cg::cp_rs1 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 701 1 Covered
|
||
|
|
bin auto[SP] 354 1 Covered
|
||
|
|
bin auto[GP] 44 1 Covered
|
||
|
|
bin auto[TP] 21 1 Covered
|
||
|
|
bin auto[T0] 146 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 61 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 33 1 Covered
|
||
|
|
bin auto[A7] 9 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 9 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 13 1 Covered
|
||
|
|
Coverpoint sw_cg::cp_rs2 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 81 1 Covered
|
||
|
|
bin auto[RA] 214 1 Covered
|
||
|
|
bin auto[SP] 70 1 Covered
|
||
|
|
bin auto[GP] 36 1 Covered
|
||
|
|
bin auto[TP] 47 1 Covered
|
||
|
|
bin auto[T0] 43 1 Covered
|
||
|
|
bin auto[T1] 38 1 Covered
|
||
|
|
bin auto[T2] 34 1 Covered
|
||
|
|
bin auto[S0] 35 1 Covered
|
||
|
|
bin auto[S1] 34 1 Covered
|
||
|
|
bin auto[A0] 33 1 Covered
|
||
|
|
bin auto[A1] 33 1 Covered
|
||
|
|
bin auto[A2] 33 1 Covered
|
||
|
|
bin auto[A3] 34 1 Covered
|
||
|
|
bin auto[A4] 33 1 Covered
|
||
|
|
bin auto[A5] 33 1 Covered
|
||
|
|
bin auto[A6] 33 1 Covered
|
||
|
|
bin auto[A7] 33 1 Covered
|
||
|
|
bin auto[S2] 34 1 Covered
|
||
|
|
bin auto[S3] 33 1 Covered
|
||
|
|
bin auto[S4] 33 1 Covered
|
||
|
|
bin auto[S5] 33 1 Covered
|
||
|
|
bin auto[S6] 33 1 Covered
|
||
|
|
bin auto[S7] 34 1 Covered
|
||
|
|
bin auto[S8] 33 1 Covered
|
||
|
|
bin auto[S9] 33 1 Covered
|
||
|
|
bin auto[S10] 34 1 Covered
|
||
|
|
bin auto[S11] 35 1 Covered
|
||
|
|
bin auto[T3] 34 1 Covered
|
||
|
|
bin auto[T4] 33 1 Covered
|
||
|
|
bin auto[T5] 80 1 Covered
|
||
|
|
bin auto[T6] 33 1 Covered
|
||
|
|
Coverpoint sw_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 1404 1 Covered
|
||
|
|
bin auto[NEGATIVE] 8 1 Covered
|
||
|
|
Coverpoint sw_cg::cp_misalign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[0] 943 1 Covered
|
||
|
|
bin auto[1] 469 1 Covered
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/jal_cg
|
||
|
|
83.33% 100 Uncovered
|
||
|
|
covered/total bins: 35 36
|
||
|
|
missing/total bins: 1 36
|
||
|
|
% Hit: 97.22% 100
|
||
|
|
Coverpoint jal_cg::cp_imm_sign 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[POSITIVE] 9 1 Covered
|
||
|
|
bin auto[NEGATIVE] 164 1 Covered
|
||
|
|
Coverpoint jal_cg::cp_rd 100.00% 100 Covered
|
||
|
|
covered/total bins: 32 32
|
||
|
|
missing/total bins: 0 32
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin auto[ZERO] 142 1 Covered
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint jal_cg::cp_rd_align 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[0] 173 1 Covered
|
||
|
|
bin auto[1] 0 1 ZERO
|
||
|
|
TYPE /riscv_instr_pkg/riscv_instr_cover_group/jalr_cg
|
||
|
|
66.14% 100 Uncovered
|
||
|
|
covered/total bins: 37 44
|
||
|
|
missing/total bins: 7 44
|
||
|
|
% Hit: 84.09% 100
|
||
|
|
Coverpoint jalr_cg::cp_imm_sign 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[POSITIVE] 31 1 Covered
|
||
|
|
bin auto[NEGATIVE] 0 1 ZERO
|
||
|
|
Coverpoint jalr_cg::cp_rd 96.87% 100 Uncovered
|
||
|
|
covered/total bins: 31 32
|
||
|
|
missing/total bins: 1 32
|
||
|
|
% Hit: 96.87% 100
|
||
|
|
bin auto[ZERO] 0 1 ZERO
|
||
|
|
bin auto[RA] 1 1 Covered
|
||
|
|
bin auto[SP] 1 1 Covered
|
||
|
|
bin auto[GP] 1 1 Covered
|
||
|
|
bin auto[TP] 1 1 Covered
|
||
|
|
bin auto[T0] 1 1 Covered
|
||
|
|
bin auto[T1] 1 1 Covered
|
||
|
|
bin auto[T2] 1 1 Covered
|
||
|
|
bin auto[S0] 1 1 Covered
|
||
|
|
bin auto[S1] 1 1 Covered
|
||
|
|
bin auto[A0] 1 1 Covered
|
||
|
|
bin auto[A1] 1 1 Covered
|
||
|
|
bin auto[A2] 1 1 Covered
|
||
|
|
bin auto[A3] 1 1 Covered
|
||
|
|
bin auto[A4] 1 1 Covered
|
||
|
|
bin auto[A5] 1 1 Covered
|
||
|
|
bin auto[A6] 1 1 Covered
|
||
|
|
bin auto[A7] 1 1 Covered
|
||
|
|
bin auto[S2] 1 1 Covered
|
||
|
|
bin auto[S3] 1 1 Covered
|
||
|
|
bin auto[S4] 1 1 Covered
|
||
|
|
bin auto[S5] 1 1 Covered
|
||
|
|
bin auto[S6] 1 1 Covered
|
||
|
|
bin auto[S7] 1 1 Covered
|
||
|
|
bin auto[S8] 1 1 Covered
|
||
|
|
bin auto[S9] 1 1 Covered
|
||
|
|
bin auto[S10] 1 1 Covered
|
||
|
|
bin auto[S11] 1 1 Covered
|
||
|
|
bin auto[T3] 1 1 Covered
|
||
|
|
bin auto[T4] 1 1 Covered
|
||
|
|
bin auto[T5] 1 1 Covered
|
||
|
|
bin auto[T6] 1 1 Covered
|
||
|
|
Coverpoint jalr_cg::cp_rd_align 50.00% 100 Uncovered
|
||
|
|
covered/total bins: 1 2
|
||
|
|
missing/total bins: 1 2
|
||
|
|
% Hit: 50.00% 100
|
||
|
|
bin auto[0] 31 1 Covered
|
||
|
|
bin auto[1] 0 1 ZERO
|
||
|
|
Coverpoint jalr_cg::cp_rs1_link 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin ra 2 1 Covered
|
||
|
|
bin t1 1 1 Covered
|
||
|
|
default bin non_link 28 Occurred
|
||
|
|
Coverpoint jalr_cg::cp_rd_link 100.00% 100 Covered
|
||
|
|
covered/total bins: 2 2
|
||
|
|
missing/total bins: 0 2
|
||
|
|
% Hit: 100.00% 100
|
||
|
|
bin ra 1 1 Covered
|
||
|
|
bin t1 1 1 Covered
|
||
|
|
default bin non_link 29 Occurred
|
||
|
|
Cross jalr_cg::cp_ras 0.00% 100 ZERO
|
||
|
|
covered/total bins: 0 4
|
||
|
|
missing/total bins: 4 4
|
||
|
|
% Hit: 0.00% 100
|
||
|
|
bin <ra,ra> 0 1 ZERO
|
||
|
|
bin <t1,ra> 0 1 ZERO
|
||
|
|
bin <ra,t1> 0 1 ZERO
|
||
|
|
bin <t1,t1> 0 1 ZERO
|
||
|
|
|
||
|
|
TOTAL COVERGROUP COVERAGE: 97.23% COVERGROUP TYPES: 37
|