45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
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// 从多个slave之间选择一个
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module obi_interconnect_slave_sel #(
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parameter int unsigned SLAVES = 3,
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parameter SLAVE_BITS = SLAVES == 1 ? 1 : $clog2(SLAVES)
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic master_req_i,
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input logic [ 31:0] master_addr_i,
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input logic [ 31:0] slave_addr_mask_i[SLAVES],
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input logic [ 31:0] slave_addr_base_i[SLAVES],
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output logic [SLAVE_BITS-1:0] slave_sel_int_o
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);
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function integer onehot2int;
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input [SLAVES-1:0] onehot;
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integer i;
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onehot2int = 0; // prevent latch behavior
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for (i = 1; i < SLAVES; i = i + 1) begin: gen_int
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if (onehot[i]) begin
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onehot2int = i;
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end
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end
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endfunction
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genvar s;
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logic [SLAVES-1:0] slave_sel_vec;
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generate
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for (s = 0; s < SLAVES; s = s + 1) begin: gen_slave_sel_vec
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assign slave_sel_vec[s] = master_req_i & ((master_addr_i & slave_addr_mask_i[s]) == slave_addr_base_i[s]);
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end
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endgenerate
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assign slave_sel_int_o = onehot2int(slave_sel_vec);
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endmodule
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