2021-07-26 01:54:38 +00:00
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#define REGBYTES 4
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#define STORE sw
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#define LOAD lw
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.section .text.vector
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.align 2
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.global trap_entry
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.global vector_table
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vector_table:
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.word illegal_instruction_handler
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.word instruction_addr_misaligned_handler
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.word ecall_handler
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.word ebreak_handler
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.word load_misaligned_handler
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.word store_misaligned_handler
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.word handle_exception_unknown
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.word handle_exception_unknown
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2021-08-19 02:22:18 +00:00
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.word timer0_irq_handler
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2021-08-13 01:35:56 +00:00
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.word uart0_irq_handler
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.word gpio0_irq_handler
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.word gpio1_irq_handler
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2021-08-19 02:22:18 +00:00
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.word i2c0_irq_handler
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2021-09-10 01:56:21 +00:00
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.word spi0_irq_handler
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.word gpio2_4_irq_handler
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.word gpio5_7_irq_handler
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.word gpio8_irq_handler
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.word gpio9_irq_handler
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.word gpio10_12_irq_handler
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.word gpio13_15_irq_handler
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.word uart1_irq_handler
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.word uart2_irq_handler
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.word i2c1_irq_handler
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.word timer1_irq_handler
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.word timer2_irq_handler
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2021-07-26 01:54:38 +00:00
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/* add your ISR here */
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.weak illegal_instruction_handler
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.weak instruction_addr_misaligned_handler
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.weak ecall_handler
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.weak ebreak_handler
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.weak load_misaligned_handler
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.weak store_misaligned_handler
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.weak handle_exception_unknown
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2021-08-19 02:22:18 +00:00
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.weak timer0_irq_handler
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2021-08-13 01:35:56 +00:00
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.weak uart0_irq_handler
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.weak gpio0_irq_handler
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.weak gpio1_irq_handler
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2021-08-19 02:22:18 +00:00
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.weak i2c0_irq_handler
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2021-09-10 01:56:21 +00:00
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.weak spi0_irq_handler
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.weak gpio2_4_irq_handler
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.weak gpio5_7_irq_handler
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.weak gpio8_irq_handler
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.weak gpio9_irq_handler
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.weak gpio10_12_irq_handler
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.weak gpio13_15_irq_handler
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.weak uart1_irq_handler
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.weak uart2_irq_handler
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.weak i2c1_irq_handler
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.weak timer1_irq_handler
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.weak timer2_irq_handler
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2021-07-26 01:54:38 +00:00
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handle_exception_unknown:
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j handle_exception_unknown
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illegal_instruction_handler:
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#ifdef SIMULATION
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call sim_ctrl_init
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la a0, illegal_instruction_msg
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jal ra, xputs
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#endif
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illegal_instruction_loop:
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j illegal_instruction_loop
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instruction_addr_misaligned_handler:
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j instruction_addr_misaligned_handler
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ecall_handler:
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j ecall_handler
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ebreak_handler:
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j ebreak_handler
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load_misaligned_handler:
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j load_misaligned_handler
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store_misaligned_handler:
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j store_misaligned_handler
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2021-08-19 02:22:18 +00:00
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timer0_irq_handler:
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j timer0_irq_handler
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2021-07-26 01:54:38 +00:00
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2021-08-13 01:35:56 +00:00
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uart0_irq_handler:
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j uart0_irq_handler
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gpio0_irq_handler:
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j gpio0_irq_handler
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gpio1_irq_handler:
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j gpio1_irq_handler
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2021-08-19 02:22:18 +00:00
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i2c0_irq_handler:
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j i2c0_irq_handler
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2021-09-10 01:56:21 +00:00
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spi0_irq_handler:
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j spi0_irq_handler
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gpio2_4_irq_handler:
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j gpio2_4_irq_handler
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gpio5_7_irq_handler:
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j gpio5_7_irq_handler
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gpio8_irq_handler:
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j gpio8_irq_handler
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gpio9_irq_handler:
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j gpio9_irq_handler
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gpio10_12_irq_handler:
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j gpio10_12_irq_handler
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gpio13_15_irq_handler:
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j gpio13_15_irq_handler
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uart1_irq_handler:
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j uart1_irq_handler
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uart2_irq_handler:
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j uart2_irq_handler
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i2c1_irq_handler:
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j i2c1_irq_handler
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timer1_irq_handler:
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j timer1_irq_handler
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timer2_irq_handler:
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j timer2_irq_handler
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2021-07-26 01:54:38 +00:00
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/* 异常和中断总入口 */
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trap_entry:
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addi sp, sp, -32*17
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sw x1, 0*4(sp)
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sw x5, 1*4(sp)
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sw x6, 2*4(sp)
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sw x7, 3*4(sp)
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sw x10, 4*4(sp)
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sw x11, 5*4(sp)
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sw x12, 6*4(sp)
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sw x13, 7*4(sp)
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sw x14, 8*4(sp)
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sw x15, 9*4(sp)
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sw x16, 10*4(sp)
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sw x17, 11*4(sp)
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sw x28, 12*4(sp)
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sw x29, 13*4(sp)
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sw x30, 14*4(sp)
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sw x31, 15*4(sp)
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/* 保存异常(中断)返回地址 */
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csrr x10, mepc
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sw x10, 16*4(sp)
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/* 使能全局中断 */
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csrrsi x0, mstatus, 0x8
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/* 读取异常(中断)号 */
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csrr a1, mcause
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/* 计算偏移地址: id * 4 */
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slli a1, a1, 2
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la a0, vector_table
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add a1, a0, a1
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/* 读取异常(中断)处理函数地址 */
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lw a1, 0(a1)
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/* 跳转到异常(中断)处理函数 */
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jalr ra, 0(a1)
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/* 恢复异常(中断)返回地址 */
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lw x10, 16*4(sp)
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csrw mepc, x10
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lw x1, 0*4(sp)
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lw x5, 1*4(sp)
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lw x6, 2*4(sp)
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lw x7, 3*4(sp)
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lw x10, 4*4(sp)
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lw x11, 5*4(sp)
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lw x12, 6*4(sp)
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lw x13, 7*4(sp)
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lw x14, 8*4(sp)
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lw x15, 9*4(sp)
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lw x16, 10*4(sp)
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lw x17, 11*4(sp)
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lw x28, 12*4(sp)
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lw x29, 13*4(sp)
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lw x30, 14*4(sp)
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lw x31, 15*4(sp)
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addi sp, sp, 32*17
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mret
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#ifdef SIMULATION
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.section .rodata
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illegal_instruction_msg:
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.string "illegal instruction exception handler entered\n"
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#endif
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