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tinyriscv/tests/isa/generated/rv32ui-p-simple.verilog

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tests: isa: add support Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-06-05 07:11:33 +00:00
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test: use csr_sstatus for test result Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-07-10 06:49:36 +00:00
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tests: isa: add support Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-06-05 07:11:33 +00:00
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@00000080
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