50 lines
2.0 KiB
Systemverilog
50 lines
2.0 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module clk_div #(
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parameter int unsigned RATIO_WIDTH = 32
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)(
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input logic clk_i, // clock
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input logic rst_ni, // asynchronous reset active low
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input logic en_i, // enable clock divider
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input logic [RATIO_WIDTH-1:0] ratio_i, // divider ratio
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output logic clk_o // divided clock out
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);
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logic [RATIO_WIDTH-1:0] counter_q;
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logic clk_q;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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clk_q <= 1'b0;
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counter_q <= '0;
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end else begin
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clk_q <= 1'b0;
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if (en_i) begin
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if (counter_q == (ratio_i - 1)) begin
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clk_q <= 1'b1;
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counter_q <= '0;
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end else begin
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counter_q <= counter_q + 1;
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end
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end
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end
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end
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assign clk_o = clk_q;
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endmodule
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