63 lines
2.2 KiB
Systemverilog
63 lines
2.2 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 静态分支预测模块
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module bpu(
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input wire clk,
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input wire rst_n,
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input wire[31:0] inst_i,
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input wire inst_valid_i,
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input wire[31:0] pc_i,
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output wire prdt_taken_o,
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output wire[31:0] prdt_addr_o
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);
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wire[6:0] opcode = inst_i[6:0];
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wire opcode_1100011 = (opcode == 7'b1100011);
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wire opcode_1101111 = (opcode == 7'b1101111);
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wire inst_type_branch = opcode_1100011;
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wire inst_jal = opcode_1101111;
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wire[31:0] inst_b_type_imm = {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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wire[31:0] inst_j_type_imm = {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
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wire prdt_taken = (inst_type_branch & inst_b_type_imm[31]) | inst_jal;
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reg[31:0] prdt_imm;
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always @ (*) begin
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prdt_imm = inst_b_type_imm;
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case (1'b1)
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inst_type_branch: prdt_imm = inst_b_type_imm;
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inst_jal: prdt_imm = inst_j_type_imm;
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default: ;
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endcase
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end
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assign prdt_taken_o = inst_valid_i ? prdt_taken : 1'b0;
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assign prdt_addr_o = pc_i + prdt_imm;
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endmodule
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