289 lines
11 KiB
Systemverilog
289 lines
11 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module i2c_master (
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input logic clk_i,
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input logic rst_ni,
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input logic enable_i,
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input logic [15:0] div_ratio_i,
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input logic read_i,
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input logic [7:0] slave_addr_i,
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input logic [7:0] slave_reg_i,
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input logic [7:0] slave_data_i,
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input logic start_i,
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output logic ready_o,
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output logic error_o,
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output logic [7:0] data_o,
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input logic scl_i,
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output logic scl_o,
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output logic scl_oe_o,
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input logic sda_i,
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output logic sda_o,
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output logic sda_oe_o
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);
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localparam S_IDLE = 6'b000001;
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localparam S_START = 6'b000010;
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localparam S_ADDR = 6'b000100;
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localparam S_REG = 6'b001000;
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localparam S_DATA = 6'b010000;
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localparam S_STOP = 6'b100000;
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logic tick;
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logic error_d, error_q;
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logic [7:0] data_d, data_q;
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logic [4:0] edge_cnt_d, edge_cnt_q;
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logic [7:0] shift_reg_d, shift_reg_q;
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logic [5:0] state_d, state_q;
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logic sda_d, sda_q;
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logic scl_d, scl_q;
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logic sda_oe_d, sda_oe_q;
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logic scl_oe_d, scl_oe_q;
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logic op_read_d, op_read_q;
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always_comb begin
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state_d = state_q;
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shift_reg_d = shift_reg_q;
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scl_d = scl_q;
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sda_oe_d = sda_oe_q;
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scl_oe_d = scl_oe_q;
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sda_d = sda_q;
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edge_cnt_d = edge_cnt_q;
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data_d = data_q;
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error_d = error_q;
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op_read_d = op_read_q;
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if (!enable_i) begin
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sda_d = 1'b0;
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sda_oe_d = 1'b0;
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scl_d = 1'b0;
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scl_oe_d = 1'b0;
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state_d = S_IDLE;
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end else begin
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case (state_q)
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S_IDLE: begin
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sda_d = 1'b1;
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sda_oe_d = 1'b1;
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scl_d = 1'b1;
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scl_oe_d = 1'b1;
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if (start_i) begin
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state_d = S_START;
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error_d = 1'b0;
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data_d = '0;
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op_read_d = 1'b0;
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end
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end
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S_START: begin
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if (tick) begin
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sda_d = 1'b0;
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edge_cnt_d = '0;
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state_d = S_ADDR;
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shift_reg_d = {slave_addr_i[7:1], op_read_q};
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end
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end
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S_ADDR: begin
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if (tick) begin
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scl_d = ~scl_q;
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edge_cnt_d = edge_cnt_q + 1'b1;
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// 下降沿释放SDA，准备接收ACK
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if (edge_cnt_q == 5'd16) begin
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sda_oe_d = 1'b0;
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// 上升沿接收ACK
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end else if (edge_cnt_q == 5'd17) begin
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// NACK
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if (sda_i) begin
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error_d = 1'b1;
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// ACK
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end else begin
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if (op_read_q) begin
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state_d = S_DATA;
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end else begin
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state_d = S_REG;
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shift_reg_d = slave_reg_i;
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end
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edge_cnt_d = '0;
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end
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// 最后一个下降沿
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end else if (edge_cnt_q == 5'd18) begin
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sda_d = 1'b0;
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sda_oe_d = 1'b1;
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// 最后一个上升沿
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end else if (edge_cnt_q == 5'd19) begin
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state_d = S_STOP;
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end else begin
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// 发数据
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if (scl_q) begin
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// 左移一位(MSB first)
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shift_reg_d = {shift_reg_q[6:0], 1'b1};
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sda_d = shift_reg_q[7];
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sda_oe_d = 1'b1;
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end
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end
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end
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end
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S_REG: begin
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if (tick) begin
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scl_d = ~scl_q;
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edge_cnt_d = edge_cnt_q + 1'b1;
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// 下降沿释放SDA，准备接收ACK
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if (edge_cnt_q == 5'd16) begin
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sda_oe_d = 1'b0;
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// 上升沿接收ACK
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end else if (edge_cnt_q == 5'd17) begin
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// NACK
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if (sda_i) begin
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error_d = 1'b1;
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// ACK
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end else begin
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// 写操作，转去S_DATA状态
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if (!read_i) begin
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state_d = S_DATA;
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shift_reg_d = slave_data_i;
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edge_cnt_d = '0;
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// 读操作，发送STOP信号
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end else begin
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op_read_d = 1'b1;
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end
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end
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// 最后一个下降沿
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end else if (edge_cnt_q == 5'd18) begin
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sda_d = 1'b0;
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sda_oe_d = 1'b1;
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// 最后一个上升沿
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end else if (edge_cnt_q == 5'd19) begin
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state_d = S_STOP;
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end else begin
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// 发数据
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if (scl_q) begin
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// 左移一位(MSB first)
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shift_reg_d = {shift_reg_q[6:0], 1'b1};
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sda_d = shift_reg_q[7];
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sda_oe_d = 1'b1;
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end
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end
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end
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end
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S_DATA: begin
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if (tick) begin
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scl_d = ~scl_q;
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edge_cnt_d = edge_cnt_q + 1'b1;
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// 下降沿释放SDA，准备接收ACK
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if (edge_cnt_q == 5'd16) begin
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sda_oe_d = 1'b0;
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// 上升沿接收ACK
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end else if (edge_cnt_q == 5'd17) begin
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// NACK
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if (sda_i ^ op_read_q) begin
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error_d = 1'b1;
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// ACK
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end else begin
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error_d = 1'b0;
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end
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op_read_d = 1'b0;
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// 最后一个下降沿
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end else if (edge_cnt_q == 5'd18) begin
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sda_d = 1'b0;
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sda_oe_d = 1'b1;
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// 最后一个上升沿
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end else if (edge_cnt_q == 5'd19) begin
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state_d = S_STOP;
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end else begin
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// 读数据
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if (op_read_q && (~scl_q)) begin
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data_d = {data_q[6:0], sda_i};
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// 发数据
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end else if ((~op_read_q) && scl_q) begin
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// 左移一位(MSB first)
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shift_reg_d = {shift_reg_q[6:0], 1'b1};
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sda_d = shift_reg_q[7];
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sda_oe_d = 1'b1;
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end
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end
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end
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end
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S_STOP: begin
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if (tick) begin
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sda_d = 1'b1;
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if (op_read_q) begin
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state_d = S_START;
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end else begin
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state_d = S_IDLE;
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end
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end
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end
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default: ;
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endcase
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end
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end
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assign scl_o = scl_q;
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assign scl_oe_o = scl_oe_q;
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assign sda_o = sda_q;
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assign sda_oe_o = sda_oe_q;
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assign data_o = data_q;
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assign ready_o = (state_q == S_IDLE);
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assign error_o = error_q;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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state_q <= S_IDLE;
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shift_reg_q <= '0;
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scl_q <= 1'b0;
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sda_q <= 1'b0;
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sda_oe_q <= 1'b0;
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scl_oe_q <= 1'b0;
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edge_cnt_q <= '0;
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data_q <= '0;
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error_q <= 1'b0;
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op_read_q <= 1'b0;
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end else begin
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state_q <= state_d;
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shift_reg_q <= shift_reg_d;
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scl_q <= scl_d;
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sda_q <= sda_d;
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sda_oe_q <= sda_oe_d;
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scl_oe_q <= scl_oe_d;
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edge_cnt_q <= edge_cnt_d;
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data_q <= data_d;
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error_q <= error_d;
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op_read_q <= op_read_d;
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end
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end
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logic [15:0] ratio = {1'b0, div_ratio_i[15:1]};
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clk_div #(
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.RATIO_WIDTH(16)
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) u_clk_div (
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.clk_i(clk_i),
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.rst_ni(rst_ni || (~((state_q == S_IDLE) && start_i))),
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.en_i(state_q != S_IDLE),
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.ratio_i(ratio),
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.clk_o(tick)
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);
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endmodule
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