72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
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// Generated register defines for flash_ctrl
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _FLASH_CTRL_REG_DEFS_
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#define _FLASH_CTRL_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define FLASH_CTRL_PARAM_REG_WIDTH 32
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#define FLASH_CTRL_BASE_ADDR (0x0E000000)
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#define FLASH_CTRL_REG(offset) (*((volatile uint32_t *)(FLASH_CTRL_BASE_ADDR + offset)))
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typedef enum {
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FLASH_OP_READ = 0,
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FLASH_OP_PROGRAM,
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FLASH_OP_ERASE,
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FLASH_OP_INIT
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} flash_op_mode_e;
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void flash_ctrl_init();
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void flash_ctrl_deinit();
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void flash_ctrl_qspi_init();
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void flash_ctrl_read(uint32_t start_addr, uint32_t *data, uint32_t len);
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uint8_t flash_ctrl_page_program(uint32_t page_addr, uint32_t *data, uint32_t len);
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uint8_t flash_ctrl_sector_erase(uint32_t sector_addr);
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// flash_ctrl control register
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#define FLASH_CTRL_CTRL_REG_OFFSET 0x0
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#define FLASH_CTRL_CTRL_REG_RESVAL 0x0
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#define FLASH_CTRL_CTRL_START_BIT 0
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#define FLASH_CTRL_CTRL_OP_MODE_MASK 0x3
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#define FLASH_CTRL_CTRL_OP_MODE_OFFSET 1
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#define FLASH_CTRL_CTRL_OP_MODE_FIELD \
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((bitfield_field32_t) { .mask = FLASH_CTRL_CTRL_OP_MODE_MASK, .index = FLASH_CTRL_CTRL_OP_MODE_OFFSET })
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#define FLASH_CTRL_CTRL_SW_CTRL_BIT 3
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#define FLASH_CTRL_CTRL_PROGRAM_INIT_BIT 4
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#define FLASH_CTRL_CTRL_WRITE_ERROR_BIT 5
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#define FLASH_CTRL_CTRL_RESERVED_MASK 0x3ffffff
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#define FLASH_CTRL_CTRL_RESERVED_OFFSET 6
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#define FLASH_CTRL_CTRL_RESERVED_FIELD \
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((bitfield_field32_t) { .mask = FLASH_CTRL_CTRL_RESERVED_MASK, .index = FLASH_CTRL_CTRL_RESERVED_OFFSET })
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// flash_ctrl address register
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#define FLASH_CTRL_ADDR_REG_OFFSET 0x4
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#define FLASH_CTRL_ADDR_REG_RESVAL 0x0
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#define FLASH_CTRL_ADDR_RW_ADDRESS_MASK 0x7fffff
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#define FLASH_CTRL_ADDR_RW_ADDRESS_OFFSET 0
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#define FLASH_CTRL_ADDR_RW_ADDRESS_FIELD \
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((bitfield_field32_t) { .mask = FLASH_CTRL_ADDR_RW_ADDRESS_MASK, .index = FLASH_CTRL_ADDR_RW_ADDRESS_OFFSET })
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#define FLASH_CTRL_ADDR_RESERVED_MASK 0x1ff
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#define FLASH_CTRL_ADDR_RESERVED_OFFSET 23
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#define FLASH_CTRL_ADDR_RESERVED_FIELD \
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((bitfield_field32_t) { .mask = FLASH_CTRL_ADDR_RESERVED_MASK, .index = FLASH_CTRL_ADDR_RESERVED_OFFSET })
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// flash_ctrl data register
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#define FLASH_CTRL_DATA_REG_OFFSET 0x8
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#define FLASH_CTRL_DATA_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _FLASH_CTRL_REG_DEFS_
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// End generated register defines for flash_ctrl
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