193 lines
6.3 KiB
Systemverilog
193 lines
6.3 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module uart_core # (
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parameter int unsigned TX_FIFO_DEPTH = 8,
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parameter int unsigned RX_FIFO_DEPTH = 8
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)(
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input logic clk_i,
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input logic rst_ni,
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output logic tx_pin_o,
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input logic rx_pin_i,
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output logic irq_o,
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input logic reg_we_i,
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input logic reg_re_i,
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input logic [31:0] reg_wdata_i,
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input logic [ 3:0] reg_be_i,
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input logic [31:0] reg_addr_i,
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output logic [31:0] reg_rdata_o
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);
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import uart_reg_pkg::*;
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uart_reg_pkg::uart_reg2hw_t reg2hw;
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uart_reg_pkg::uart_hw2reg_t hw2reg;
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logic tx_enable;
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logic rx_enable;
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logic [15:0] baud_div;
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logic tx_fifo_empty_int_en;
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logic rx_fifo_not_empty_int_en;
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logic tx_fifo_rst;
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logic rx_fifo_rst;
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logic tx_idle;
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logic rx_idle;
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logic rx_error;
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logic tx_fifo_full;
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logic rx_fifo_full;
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logic tx_fifo_empty;
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logic rx_fifo_empty;
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logic tx_we;
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logic [7:0] tx_wdata;
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logic [7:0] rx_rdata;
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logic rx_rvalid;
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logic tx_fifo_pop;
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logic rx_fifo_pop;
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logic tx_fifo_push;
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logic rx_fifo_push;
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logic [7:0] tx_fifo_data_out;
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logic [7:0] rx_fifo_data_out;
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logic [7:0] tx_fifo_data_in;
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logic [7:0] rx_fifo_data_in;
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// 波特率分频系数
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assign baud_div = reg2hw.ctrl.baud_div.q;
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// TX
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assign tx_enable = reg2hw.ctrl.tx_en.q;
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assign tx_fifo_empty_int_en = reg2hw.ctrl.tx_fifo_empty_int_en.q;
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// 写1清TX fifo
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assign tx_fifo_rst = reg2hw.ctrl.tx_fifo_rst.qe & reg2hw.ctrl.tx_fifo_rst.q;
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assign hw2reg.status.txidle.d = tx_enable ? (tx_idle & tx_fifo_empty) : 1'b1;
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assign hw2reg.status.txfull.d = tx_fifo_full;
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assign hw2reg.status.txempty.d = tx_fifo_empty;
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// TX开始发送数据
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assign tx_we = tx_enable & (!tx_fifo_empty) & tx_idle;
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// 要发送的数据
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assign tx_wdata = tx_fifo_data_out;
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// 取出fifo数据
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assign tx_fifo_pop = tx_enable & (!tx_fifo_empty) & tx_idle;
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// 可以先push完数据再使能TX
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assign tx_fifo_push = reg2hw.txdata.qe & (!tx_fifo_full);
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// 要压入fifo的数据
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assign tx_fifo_data_in = reg2hw.txdata.q;
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// RX
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assign rx_enable = reg2hw.ctrl.rx_en.q;
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assign rx_fifo_not_empty_int_en = reg2hw.ctrl.rx_fifo_not_empty_int_en.q;
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// 写1清RX fifo
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assign rx_fifo_rst = reg2hw.ctrl.rx_fifo_rst.qe & reg2hw.ctrl.rx_fifo_rst.q;
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assign hw2reg.status.rxidle.d = rx_enable ? rx_idle : 1'b1;
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assign hw2reg.status.rxfull.d = rx_fifo_full;
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assign hw2reg.status.rxempty.d = rx_fifo_empty;
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assign hw2reg.rxdata.d = rx_fifo_data_out;
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// 将接收到的数据压入fifo
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assign rx_fifo_push = (~rx_fifo_full) & rx_rvalid;
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// 要压入的数据
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assign rx_fifo_data_in = rx_rdata;
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// 可以在不使能RX的情况下直接读RX fifo里面的数据
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assign rx_fifo_pop = reg2hw.rxdata.re & (~rx_fifo_empty);
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// 中断信号
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assign irq_o = (tx_enable & tx_fifo_empty_int_en & tx_fifo_empty) |
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(rx_enable & rx_fifo_not_empty_int_en & (~rx_fifo_empty));
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// TX byte
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uart_tx u_uart_tx (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.enable_i (tx_enable),
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.parity_en_i(1'b0),
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.parity_i (1'b1),
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.we_i (tx_we),
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.wdata_i (tx_wdata),
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.div_ratio_i(baud_div),
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.idle_o (tx_idle),
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.tx_bit_o (tx_pin_o)
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);
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// TX FIFO
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sync_fifo #(
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.DATA_WIDTH(8),
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.DEPTH(TX_FIFO_DEPTH)
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) u_tx_fifo (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i (tx_fifo_rst),
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.testmode_i (1'b0),
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.full_o (tx_fifo_full),
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.empty_o (tx_fifo_empty),
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.usage_o (),
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.data_i (tx_fifo_data_in),
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.push_i (tx_fifo_push),
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.data_o (tx_fifo_data_out),
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.pop_i (tx_fifo_pop)
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);
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// RX byte
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uart_rx u_uart_rx (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.enable_i (rx_enable),
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.parity_en_i (1'b0),
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.parity_odd_i (1'b1),
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.div_ratio_i (baud_div),
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.rx_i (rx_pin_i),
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.idle_o (rx_idle),
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.err_o (rx_error),
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.rdata_o (rx_rdata),
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.rvalid_o (rx_rvalid)
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);
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// RX FIFO
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sync_fifo #(
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.DATA_WIDTH(8),
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.DEPTH(RX_FIFO_DEPTH)
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) u_rx_fifo (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i (rx_fifo_rst),
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.testmode_i (1'b0),
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.full_o (rx_fifo_full),
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.empty_o (rx_fifo_empty),
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.usage_o (),
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.data_i (rx_fifo_data_in),
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.push_i (rx_fifo_push),
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.data_o (rx_fifo_data_out),
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.pop_i (rx_fifo_pop)
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);
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uart_reg_top u_uart_reg_top (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.reg2hw (reg2hw),
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.hw2reg (hw2reg),
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.reg_we (reg_we_i),
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.reg_re (reg_re_i),
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.reg_wdata (reg_wdata_i),
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.reg_be (reg_be_i),
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.reg_addr (reg_addr_i),
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.reg_rdata (reg_rdata_o)
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);
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endmodule
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