93 lines
3.1 KiB
Coq
93 lines
3.1 KiB
Coq
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/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 通用寄存器模块
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module gpr_reg(
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input wire clk,
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input wire rst_n,
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input wire we_i, // 写寄存器使能
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input wire[4:0] waddr_i, // 写寄存器地址
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input wire[31:0] wdata_i, // 写寄存器数据
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input wire[4:0] raddr1_i, // 读寄存器1地址
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output wire[31:0] rdata1_o, // 读寄存器1数据
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input wire[4:0] raddr2_i, // 读寄存器2地址
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output wire[31:0] rdata2_o // 读寄存器2数据
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);
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wire[32-1:0] regs[32-1:0];
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wire[32-1:0] we;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1) begin
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// x0 cannot be wrote since it is constant-zeros
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if (i == 0) begin
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assign we[i] = 1'b0;
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assign regs[i] = 32'h0;
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end else begin
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assign we[i] = we_i & (waddr_i == i);
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gen_en_dffnr #(32) rf_dff(clk, we[i], wdata_i, regs[i]);
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end
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end
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endgenerate
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assign rdata1_o = regs[raddr1_i];
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assign rdata2_o = regs[raddr2_i];
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// for debug
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wire[31:0] ra = regs[1];
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wire[31:0] sp = regs[2];
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wire[31:0] gp = regs[3];
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wire[31:0] tp = regs[4];
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wire[31:0] t0 = regs[5];
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wire[31:0] t1 = regs[6];
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wire[31:0] t2 = regs[7];
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wire[31:0] s0 = regs[8];
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wire[31:0] fp = regs[8];
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wire[31:0] s1 = regs[9];
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wire[31:0] a0 = regs[10];
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wire[31:0] a1 = regs[11];
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wire[31:0] a2 = regs[12];
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wire[31:0] a3 = regs[13];
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wire[31:0] a4 = regs[14];
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wire[31:0] a5 = regs[15];
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wire[31:0] a6 = regs[16];
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wire[31:0] a7 = regs[17];
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wire[31:0] s2 = regs[18];
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wire[31:0] s3 = regs[19];
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wire[31:0] s4 = regs[20];
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wire[31:0] s5 = regs[21];
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wire[31:0] s6 = regs[22];
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wire[31:0] s7 = regs[23];
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wire[31:0] s8 = regs[24];
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wire[31:0] s9 = regs[25];
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wire[31:0] s10 = regs[26];
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wire[31:0] s11 = regs[27];
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wire[31:0] t3 = regs[28];
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wire[31:0] t4 = regs[29];
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wire[31:0] t5 = regs[30];
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wire[31:0] t6 = regs[31];
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endmodule
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