2021-03-31 10:00:19 +00:00
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// core local interruptor module
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// <20><><EFBFBD><EFBFBD><EFBFBD>жϹ<D0B6><CFB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٲ<EFBFBD>ģ<EFBFBD><C4A3>
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module clint(
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input wire clk,
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input wire rst_n,
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// from core
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input wire[`INT_WIDTH-1:0] int_flag_i, // <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
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// from exu
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input wire inst_ecall_i, // ecallָ<6C><D6B8>
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input wire inst_ebreak_i, // ebreakָ<6B><D6B8>
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input wire inst_mret_i, // mretָ<74><D6B8>
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input wire[31:0] inst_addr_i, // ָ<><D6B8><EFBFBD><EFBFBD>ַ
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input wire jump_flag_i,
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input wire mem_access_misaligned_i,
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// from csr_reg
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input wire[31:0] csr_mtvec_i, // mtvec<65>Ĵ<EFBFBD><C4B4><EFBFBD>
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input wire[31:0] csr_mepc_i, // mepc<70>Ĵ<EFBFBD><C4B4><EFBFBD>
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input wire[31:0] csr_mstatus_i, // mstatus<75>Ĵ<EFBFBD><C4B4><EFBFBD>
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// to csr_reg
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output reg csr_we_o, // дCSR<53>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>־
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output reg[31:0] csr_waddr_o, // дCSR<53>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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output reg[31:0] csr_wdata_o, // дCSR<53>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// to pipe_ctrl
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output wire stall_flag_o, // <20><>ˮ<EFBFBD><CBAE><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>־
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output wire[31:0] int_addr_o, // <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ڵ<EFBFBD>ַ
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output wire int_assert_o // <20>жϱ<D0B6>־
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);
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// <20>ж<EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD>
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localparam S_INT_IDLE = 4'b0001;
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localparam S_INT_SYNC_ASSERT = 4'b0010;
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localparam S_INT_ASYNC_ASSERT = 4'b0100;
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localparam S_INT_MRET = 4'b1000;
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// дCSR<53>Ĵ<EFBFBD><C4B4><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD>
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localparam S_CSR_IDLE = 5'b00001;
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localparam S_CSR_MSTATUS = 5'b00010;
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localparam S_CSR_MEPC = 5'b00100;
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localparam S_CSR_MSTATUS_MRET = 5'b01000;
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localparam S_CSR_MCAUSE = 5'b10000;
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reg[3:0] int_state;
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reg[4:0] csr_state;
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reg[31:0] inst_addr;
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reg[31:0] cause;
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wire global_int_en = csr_mstatus_i[3];
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assign stall_flag_o = ((int_state != S_INT_IDLE) | (csr_state != S_CSR_IDLE))? 1'b1: 1'b0;
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// <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˮ<EFBFBD><CBAE><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD>
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wire pc_state_jump_flag;
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gen_rst_0_dff #(1) pc_state_dff(clk, rst_n, jump_flag_i, pc_state_jump_flag);
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wire if_state_jump_flag;
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gen_rst_0_dff #(1) if_state_dff(clk, rst_n, pc_state_jump_flag, if_state_jump_flag);
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wire id_state_jump_flag;
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gen_rst_0_dff #(1) id_state_dff(clk, rst_n, if_state_jump_flag, id_state_jump_flag);
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wire ex_state_jump_flag;
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gen_rst_0_dff #(1) ex_state_dff(clk, rst_n, id_state_jump_flag, ex_state_jump_flag);
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wire[3:0] state_jump_flag = {pc_state_jump_flag, if_state_jump_flag, id_state_jump_flag, ex_state_jump_flag};
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˮ<EFBFBD><CBAE>û<EFBFBD>г<EFBFBD>ˢ<EFBFBD><CBA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ж<EFBFBD>
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wire inst_addr_valid = (~(|state_jump_flag)) | ex_state_jump_flag;
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// <20>ж<EFBFBD><D0B6>ٲ<EFBFBD><D9B2><EFBFBD>
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always @ (*) begin
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// ͬ<><CDAC><EFBFBD>ж<EFBFBD>
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if (inst_ecall_i | inst_ebreak_i | mem_access_misaligned_i) begin
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int_state = S_INT_SYNC_ASSERT;
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// <20>첽<EFBFBD>ж<EFBFBD>
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end else if ((int_flag_i != `INT_NONE) & global_int_en & inst_addr_valid) begin
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int_state = S_INT_ASYNC_ASSERT;
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// <20>жϷ<D0B6><CFB7><EFBFBD>
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end else if (inst_mret_i) begin
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int_state = S_INT_MRET;
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// <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>Ӧ
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end else begin
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int_state = S_INT_IDLE;
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end
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end
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// дCSR<53>Ĵ<EFBFBD><C4B4><EFBFBD>״̬<D7B4>л<EFBFBD>
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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csr_state <= S_CSR_IDLE;
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cause <= 32'h0;
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inst_addr <= 32'h0;
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end else begin
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case (csr_state)
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S_CSR_IDLE: begin
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case (int_state)
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// ͬ<><CDAC><EFBFBD>ж<EFBFBD>
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S_INT_SYNC_ASSERT: begin
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csr_state <= S_CSR_MEPC;
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// <20><><EFBFBD>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ὣ<EFBFBD>жϷ<D0B6><CFB7>ص<EFBFBD>ַ<EFBFBD><D6B7>4
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inst_addr <= inst_addr_i;
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cause <= inst_ebreak_i? 32'd3:
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inst_ecall_i? 32'd11:
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mem_access_misaligned_i? 32'd4:
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32'd10;
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end
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// <20>첽<EFBFBD>ж<EFBFBD>
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S_INT_ASYNC_ASSERT: begin
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csr_state <= S_CSR_MEPC;
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inst_addr <= inst_addr_i;
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// <20><>ʱ<EFBFBD><CAB1><EFBFBD>ж<EFBFBD>
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cause <= 32'h80000004;
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end
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// <20>жϷ<D0B6><CFB7><EFBFBD>
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S_INT_MRET: begin
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csr_state <= S_CSR_MSTATUS_MRET;
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end
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endcase
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end
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S_CSR_MEPC: begin
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csr_state <= S_CSR_MSTATUS;
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end
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S_CSR_MSTATUS: begin
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csr_state <= S_CSR_MCAUSE;
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end
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S_CSR_MCAUSE: begin
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csr_state <= S_CSR_IDLE;
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end
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S_CSR_MSTATUS_MRET: begin
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csr_state <= S_CSR_IDLE;
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end
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default: begin
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csr_state <= S_CSR_IDLE;
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end
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endcase
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end
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end
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// <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>ź<EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>CSR<53>Ĵ<EFBFBD><C4B4><EFBFBD>
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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csr_we_o <= 1'b0;
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csr_waddr_o <= 32'h0;
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csr_wdata_o <= 32'h0;
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end else begin
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case (csr_state)
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// <20><>mepc<70>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>Ϊ<EFBFBD><CEAA>ǰָ<C7B0><D6B8><EFBFBD><EFBFBD>ַ
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S_CSR_MEPC: begin
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csr_we_o <= 1'b1;
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csr_waddr_o <= {20'h0, `CSR_MEPC};
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csr_wdata_o <= inst_addr;
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end
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// д<>жϲ<D0B6><CFB2><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>
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S_CSR_MCAUSE: begin
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csr_we_o <= 1'b1;
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csr_waddr_o <= {20'h0, `CSR_MCAUSE};
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csr_wdata_o <= cause;
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end
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// <20>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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S_CSR_MSTATUS: begin
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csr_we_o <= 1'b1;
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csr_waddr_o <= {20'h0, `CSR_MSTATUS};
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csr_wdata_o <= {csr_mstatus_i[31:4], 1'b0, csr_mstatus_i[2:0]};
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end
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// <20>жϷ<D0B6><CFB7><EFBFBD>
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S_CSR_MSTATUS_MRET: begin
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csr_we_o <= 1'b1;
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csr_waddr_o <= {20'h0, `CSR_MSTATUS};
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csr_wdata_o <= {csr_mstatus_i[31:4], csr_mstatus_i[7], csr_mstatus_i[2:0]};
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end
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default: begin
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csr_we_o <= 1'b0;
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csr_waddr_o <= 32'h0;
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csr_wdata_o <= 32'h0;
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end
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endcase
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end
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end
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reg in_int_context;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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in_int_context <= 1'b0;
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end else begin
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if (csr_state == S_CSR_MSTATUS_MRET) begin
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in_int_context <= 1'b0;
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end else if (csr_state != S_CSR_IDLE) begin
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in_int_context <= 1'b1;
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end
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end
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end
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assign int_assert_o = (csr_state == S_CSR_MCAUSE) | (csr_state == S_CSR_MSTATUS_MRET);
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assign int_addr_o = (csr_state == S_CSR_MCAUSE)? csr_mtvec_i:
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(csr_state == S_CSR_MSTATUS_MRET)? csr_mepc_i:
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32'h0;
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endmodule
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