98 lines
3.1 KiB
Coq
98 lines
3.1 KiB
Coq
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 32 bits count up timer module
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module timer (
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input wire clk,
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input wire rst,
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input wire[31:0] wdata,
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input wire[31:0] waddr,
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input wire[31:0] raddr,
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input wire we,
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output reg[31:0] rdata,
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output wire int_sig
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);
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// timer expired value
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// addr: 0x10000008
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reg[31:0] timer_value;
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// timer current count, read only
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// addr: 0x10000004
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reg[31:0] timer_count;
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// [0]: timer enable
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// [1]: timer int enable
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// [2]: timer int pending, write 1 to clear it
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// addr: 0x10000000
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reg[31:0] timer_ctrl;
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assign int_sig = ((timer_ctrl[0] == 1'b1) && (timer_ctrl[1] == 1'b1) && (timer_ctrl[2] == 1'b1)) ? 1'b1 : 1'b0;
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// write timer regs
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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timer_count <= 32'h0;
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timer_value <= 32'h0;
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timer_ctrl <= 32'h0;
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end else begin
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if (timer_ctrl[0] == 1'b1) begin
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timer_count <= timer_count + 1'b1;
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if (timer_count == timer_value) begin
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timer_ctrl[2] <= 1'b1;
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timer_count <= 32'h0;
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end
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end
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if (we == 1'b1) begin
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if (waddr == 32'h10000008) begin
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timer_value <= wdata;
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end else if (waddr == 32'h10000000) begin
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if (wdata[2] == 1'b0) begin
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timer_ctrl <= wdata;
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// write 1 to clear pending
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end else begin
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timer_ctrl <= {wdata[31:3], 1'b0, wdata[1:0]};
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end
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end
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end
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end
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end
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// read timer regs
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always @ (*) begin
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if (rst == 1'b0) begin
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rdata <= 32'h0;
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end else begin
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if (raddr == 32'h10000008) begin
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rdata <= timer_value;
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end else if (raddr == 32'h10000000) begin
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rdata <= timer_ctrl;
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end else if (raddr == 32'h10000004) begin
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rdata <= timer_count;
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end else begin
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rdata <= 32'h0;
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end
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end
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end
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endmodule
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