80 lines
2.8 KiB
Systemverilog
80 lines
2.8 KiB
Systemverilog
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Write enable and data arbitration logic for register slice conforming to Comportibility guide.
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module prim_subreg_arb #(
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parameter int DW = 32 ,
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parameter SWACCESS = "RW" // {RW, RO, WO, W1C, W1S, W0C, RC}
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) (
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// From SW: valid for RW, WO, W1C, W1S, W0C, RC.
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// In case of RC, top connects read pulse to we.
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input we,
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input [DW-1:0] wd,
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// From HW: valid for HRW, HWO.
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input de,
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input [DW-1:0] d,
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// From register: actual reg value.
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input [DW-1:0] q,
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// To register: actual write enable and write data.
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output logic wr_en,
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output logic [DW-1:0] wr_data
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);
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if ((SWACCESS == "RW") || (SWACCESS == "WO")) begin : gen_w
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assign wr_en = we | de;
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assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
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// Unused q - Prevent lint errors.
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logic [DW-1:0] unused_q;
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assign unused_q = q;
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end else if (SWACCESS == "RO") begin : gen_ro
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assign wr_en = de;
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assign wr_data = d;
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// Unused we, wd, q - Prevent lint errors.
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logic unused_we;
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logic [DW-1:0] unused_wd;
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logic [DW-1:0] unused_q;
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assign unused_we = we;
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assign unused_wd = wd;
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assign unused_q = q;
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end else if (SWACCESS == "W1S") begin : gen_w1s
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// If SWACCESS is W1S, then assume hw tries to clear.
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// So, give a chance HW to clear when SW tries to set.
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// If both try to set/clr at the same bit pos, SW wins.
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assign wr_en = we | de;
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assign wr_data = (de ? d : q) | (we ? wd : '0);
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end else if (SWACCESS == "W1C") begin : gen_w1c
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// If SWACCESS is W1C, then assume hw tries to set.
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// So, give a chance HW to set when SW tries to clear.
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// If both try to set/clr at the same bit pos, SW wins.
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assign wr_en = we | de;
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assign wr_data = (de ? d : q) & (we ? ~wd : '1);
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end else if (SWACCESS == "W0C") begin : gen_w0c
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assign wr_en = we | de;
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assign wr_data = (de ? d : q) & (we ? wd : '1);
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end else if (SWACCESS == "RC") begin : gen_rc
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// This swtype is not recommended but exists for compatibility.
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// WARN: we signal is actually read signal not write enable.
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assign wr_en = we | de;
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assign wr_data = (de ? d : q) & (we ? '0 : '1);
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// Unused wd - Prevent lint errors.
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logic [DW-1:0] unused_wd;
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assign unused_wd = wd;
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end else begin : gen_hw
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assign wr_en = de;
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assign wr_data = d;
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// Unused we, wd, q - Prevent lint errors.
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logic unused_we;
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logic [DW-1:0] unused_wd;
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logic [DW-1:0] unused_q;
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assign unused_we = we;
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assign unused_wd = wd;
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assign unused_q = q;
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end
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endmodule
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