61 lines
2.0 KiB
Systemverilog
61 lines
2.0 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module timer_top (
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input logic clk_i,
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input logic rst_ni,
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output logic irq_o,
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// OBI总线接口信号
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input logic req_i,
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input logic we_i,
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input logic [ 3:0] be_i,
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input logic [31:0] addr_i,
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input logic [31:0] data_i,
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output logic [31:0] data_o
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);
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logic re;
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logic we;
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logic [31:0] addr;
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logic [31:0] reg_rdata;
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// 读信号
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assign re = req_i & (!we_i);
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// 写信号
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assign we = req_i & we_i;
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// 去掉基地址
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assign addr = {16'h0, addr_i[15:0]};
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timer_core u_timer_core (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.irq_o (irq_o),
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.reg_we_i (we),
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.reg_re_i (re),
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.reg_wdata_i(data_i),
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.reg_be_i (be_i),
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.reg_addr_i (addr),
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.reg_rdata_o(reg_rdata)
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);
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always_ff @(posedge clk_i) begin
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data_o <= reg_rdata;
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end
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endmodule
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